rockchip: clk: remove RATE_TO_DIV

Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 514ea88f3bd953356f507c4a79cc49d128ed1d15..83f4ae6ca394f5dad546c9037573f617b614d642 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -249,8 +249,9 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
        /* mmc clock auto divide 2 in internal */
        src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
 
-       if (src_clk_div > 0x7f) {
+       if (src_clk_div > 128) {
                src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
+               assert(src_clk_div - 1 < 128);
                mux = EMMC_SEL_24M;
        } else {
                mux = EMMC_SEL_GPLL;

diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c
index cbf31d7de1af6ee8d9a8f1a1ce242959c32e9cd2..8c2c9bc1d87ca0350977f8e50863a3105d2efdaa 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -71,9 +71,6 @@ enum {
        SOCSTS_GPLL_LOCK        = 1 << 8,
 };
 
-#define RATE_TO_DIV(input_rate, output_rate) \
-       ((input_rate) / (output_rate) - 1);
-
 #define DIV_TO_RATE(input_rate, div)   ((input_rate) / ((div) + 1))
 
 #define PLL_DIVISORS(hz, _nr, _no) {\
@@ -297,7 +294,7 @@ static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
 
        debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
        /* mmc clock defaulg div 2 internal, need provide double in cru */
-       src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
+       src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1;
        assert(src_clk_div <= 0x3f);
 
        switch (periph) {
@@ -351,8 +348,9 @@ static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate,
 static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate,
                                  int periph, uint freq)
 {
-       int src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+       int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
 
+       assert(src_clk_div < 128);
        switch (periph) {
        case SCLK_SPI0:
                assert(src_clk_div <= SPI0_DIV_MASK);
@@ -401,8 +399,8 @@ static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf,
         * reparent aclk_cpu_pre from apll to gpll
         * set up dependent divisors for PCLK/HCLK and ACLK clocks.
         */
-       aclk_div = RATE_TO_DIV(GPLL_HZ, CPU_ACLK_HZ);
-       assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
+       aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1;
+       assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
 
        rk_clrsetreg(&cru->cru_clksel_con[0],
                     CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT |

diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index a1a0aff8a98d77dd8c5437db2b08c28e280be544..d7f6a3c313e6c86143dc3931fc00196981d8b534 100644 (file)
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -26,9 +26,6 @@ enum {
        OUTPUT_MIN_HZ   = 24 * 1000000,
 };
 
-#define RATE_TO_DIV(input_rate, output_rate) \
-       ((input_rate) / (output_rate) - 1);
-
 #define DIV_TO_RATE(input_rate, div)   ((input_rate) / ((div) + 1))
 
 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
@@ -253,8 +250,9 @@ static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
        /* mmc clock defaulg div 2 internal, need provide double in cru */
        src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
 
-       if (src_clk_div > 0x7f) {
+       if (src_clk_div > 128) {
                src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
+               assert(src_clk_div - 1 < 128);
                mux = EMMC_SEL_24M;
        } else {
                mux = EMMC_SEL_GPLL;

diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index adb4e1cd9df70a12e9d554edb93ffae1afb51182..478195b10b0eb6175b86a8a0b599c1011af3671e 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -118,9 +118,6 @@ enum {
        SOCSTS_NPLL_LOCK        = 1 << 9,
 };
 
-#define RATE_TO_DIV(input_rate, output_rate) \
-       ((input_rate) / (output_rate) - 1);
-
 #define DIV_TO_RATE(input_rate, div)   ((input_rate) / ((div) + 1))
 
 #define PLL_DIVISORS(hz, _nr, _no) {\
@@ -535,6 +532,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 
        if (src_clk_div > 0x3f) {
                src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
+               assert(src_clk_div < 0x40);
                mux = EMMC_PLL_SELECT_24MHZ;
                assert((int)EMMC_PLL_SELECT_24MHZ ==
                       (int)MMC0_PLL_SELECT_24MHZ);
@@ -608,7 +606,8 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
        int src_clk_div;
 
        debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
-       src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+       src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
+       assert(src_clk_div < 128);
        switch (periph) {
        case SCLK_SPI0:
                rk_clrsetreg(&cru->cru_clksel_con[25],

diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 9ef5badf56da0fcc540347e4a022c9d402341b12..2be1f572d7212a166cf96680fb26b71464d360ba 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -39,9 +39,6 @@ struct pll_div {
 #define GPLL_HZ                (576 * 1000 * 1000)
 #define CPLL_HZ                (400 * 1000 * 1000)
 
-#define RATE_TO_DIV(input_rate, output_rate) \
-               ((input_rate) / (output_rate) - 1);
-
 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
 
 #define PLL_DIVISORS(hz, _nr, _no) { \

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index ec149c8be80bcf3b78f05cb31c77f9bbb712879d..3edafea140073a5f7c53df3af07a956cb195ae8f 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -676,8 +676,8 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
        const struct spi_clkreg *spiclk = NULL;
        int src_clk_div;
 
-       src_clk_div = RATE_TO_DIV(GPLL_HZ, hz);
-       assert(src_clk_div < 127);
+       src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
+       assert(src_clk_div < 128);
 
        switch (clk_id) {
        case SCLK_SPI1 ... SCLK_SPI5:
@@ -782,9 +782,10 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
                /* mmc clock defaulg div 2 internal, provide double in cru */
                src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
 
-               if (src_clk_div > 127) {
+               if (src_clk_div > 128) {
                        /* use 24MHz source for 400KHz clock */
                        src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
+                       assert(src_clk_div - 1 < 128);
                        rk_clrsetreg(&cru->clksel_con[16],
                                     CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
                                     CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
@@ -798,8 +799,8 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
                break;
        case SCLK_EMMC:
                /* Select aclk_emmc source from GPLL */
-               src_clk_div = GPLL_HZ / aclk_emmc;
-               assert(src_clk_div - 1 < 31);
+               src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc);
+               assert(src_clk_div - 1 < 32);
 
                rk_clrsetreg(&cru->clksel_con[21],
                             ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
@@ -807,8 +808,8 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
                             (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
 
                /* Select clk_emmc source from GPLL too */
-               src_clk_div = GPLL_HZ / set_rate;
-               assert(src_clk_div - 1 < 127);
+               src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
+               assert(src_clk_div - 1 < 128);
 
                rk_clrsetreg(&cru->clksel_con[22],
                             CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,

diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c
index 818293dfe87ad178aaed0ab2fd0fbb9f4c95516a..cf966bbdc339924eba4ac8e73b630f41da53d5e2 100644 (file)
--- a/drivers/clk/rockchip/clk_rv1108.c
+++ b/drivers/clk/rockchip/clk_rv1108.c
@@ -25,9 +25,6 @@ enum {
        OUTPUT_MIN_HZ   = 24 * 1000000,
 };
 
-#define RATE_TO_DIV(input_rate, output_rate) \
-       ((input_rate) / (output_rate) - 1);
-
 #define DIV_TO_RATE(input_rate, div)   ((input_rate) / ((div) + 1))
 
 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\