ARM: dts: at91: Add RSTC node

Add node for RSTC.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>

diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
index be44519934b9c998fa6cfe05bdde1eb9f3db3308..733cc5cec95cc4bb1bd1d0288accf1dc4b7b7a13 100644 (file)
--- a/arch/arm/dts/sam9x60.dtsi
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -223,6 +223,12 @@
                                status = "okay";
                        };
 
+                       reset_controller: rstc@fffffe00 {
+                               compatible = "microchip,sam9x60-rstc";
+                               reg = <0xfffffe00 0x10>;
+                               clocks = <&clk32 0>;
+                       };
+
                        pit: timer@fffffe40 {
                                compatible = "atmel,at91sam9260-pit";
                                reg = <0xfffffe40 0x10>;

diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi
index b7c261ebe9ead8d601d09d7fb827883fcbf66553..7015bd7f6d1200e3afb1e7b53975fd2e5d4e0e6f 100644 (file)
--- a/arch/arm/dts/sama7g5.dtsi
+++ b/arch/arm/dts/sama7g5.dtsi
@@ -232,6 +232,13 @@
                        clocks = <&clk32k 0>;
                };
 
+               reset_controller: rstc@e001d000 {
+                       compatible = "microchip,sama7g5-rstc", "microchip,sam9x60-rstc";
+                       reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>;
+                       #reset-cells = <1>;
+                       clocks = <&clk32k 0>;
+               };
+
                clk32k: clock-controller@e001d050 {
                        compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc";
                        reg = <0xe001d050 0x4>;