arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port

Now that PCI Bridge (PCIe Root Port) for Aardvark is emulated in U-Boot,
add support for handling and propagation of CRSSVE bit.

When CRSSVE bit is unset (default), driver has to reissue config
read/write request on CRS response.

CRSSVE bit is supported only when CRSVIS bit is provided in read-only
Root Capabilities register. So manually inject this CRSVIS bit into read
response for that register.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 2481cbea526999681519f29b9b790ae712d33add..591bc8b48cd21c1a71fffe8ef4699ac6c107cbb9 100644 (file)
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -41,6 +41,7 @@
 #define     PCIE_CORE_CMD_MEM_IO_REQ_EN                                BIT(2)
 #define PCIE_CORE_DEV_REV_REG                                  0x8
 #define PCIE_CORE_EXP_ROM_BAR_REG                              0x30
+#define PCIE_CORE_PCIEXP_CAP_OFF                               0xc0
 #define PCIE_CORE_DEV_CTRL_STATS_REG                           0xc8
 #define     PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE       (0 << 4)
 #define     PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE             (0 << 11)
@@ -201,6 +202,7 @@ struct pcie_advk {
        struct udevice *dev;
        struct gpio_desc reset_gpio;
        u32            cfgcache[0x34 - 0x10];
+       bool           cfgcrssve;
 };
 
 static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
@@ -413,6 +415,18 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
                        data |= PCI_HEADER_TYPE_BRIDGE << 16;
                }
 
+               if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL) {
+                       /* CRSSVE bit is stored only in cache */
+                       if (pcie->cfgcrssve)
+                               data |= PCI_EXP_RTCTL_CRSSVE;
+               }
+
+               if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF +
+                                    (PCI_EXP_RTCAP & ~3)) {
+                       /* CRS is emulated below, so set CRSVIS capability */
+                       data |= PCI_EXP_RTCAP_CRSVIS << 16;
+               }
+
                *valuep = pci_conv_32_to_size(data, offset, size);
 
                return 0;
@@ -423,13 +437,14 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
         * OS is allowed only for 4-byte PCI_VENDOR_ID config read request and
         * only when CRSSVE bit in Root Port PCIe device is enabled. In all
         * other error PCIe Root Complex must return all-ones.
-        * Aardvark HW does not have Root Port PCIe device and U-Boot does not
-        * implement emulation of this device.
+        *
         * U-Boot currently does not support handling of CRS return value for
         * PCI_VENDOR_ID config read request and also does not set CRSSVE bit.
-        * Therefore disable returning CRS response for now.
+        * So it means that pcie->cfgcrssve is false. But the code is prepared
+        * for returning CRS, so that if U-Boot does support CRS in the future,
+        * it will work for Aardvark.
         */
-       allow_crs = false;
+       allow_crs = pcie->cfgcrssve;
 
        if (advk_readl(pcie, PIO_START)) {
                dev_err(pcie->dev,
@@ -583,6 +598,9 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
                    (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))
                        pcie->sec_busno = (data >> 8) & 0xff;
 
+               if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL)
+                       pcie->cfgcrssve = data & PCI_EXP_RTCTL_CRSSVE;
+
                return 0;
        }
 

diff --git a/include/pci.h b/include/pci.h
index 11009a2f787a22da435f86132a1ff85fbec39c3d..797f224e2fc4d3851622bec9ac23d0b4585ff4a8 100644 (file)
--- a/include/pci.h
+++ b/include/pci.h
@@ -495,6 +495,10 @@
 #define  PCI_EXP_LNKSTA_DLLLA  0x2000  /* Data Link Layer Link Active */
 #define PCI_EXP_SLTCAP         20      /* Slot Capabilities */
 #define  PCI_EXP_SLTCAP_PSN    0xfff80000 /* Physical Slot Number */
+#define PCI_EXP_RTCTL          28      /* Root Control */
+#define  PCI_EXP_RTCTL_CRSSVE  0x0010  /* CRS Software Visibility Enable */
+#define PCI_EXP_RTCAP          30      /* Root Capabilities */
+#define  PCI_EXP_RTCAP_CRSVIS  0x0001  /* CRS Software Visibility capability */
 #define PCI_EXP_DEVCAP2                36      /* Device Capabilities 2 */
 #define  PCI_EXP_DEVCAP2_ARI   0x00000020 /* ARI Forwarding Supported */
 #define PCI_EXP_DEVCTL2                40      /* Device Control 2 */