pcie_imx: Add mx6solox support

Let PCI on mx6solox also be supported.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index a861e655ead742ae83068c927a873708ad955b66..52136f7a22d807c7e69c76aa81c2a25e26a4d693 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -599,6 +599,7 @@ int enable_pcie_clock(void)
        struct anatop_regs *anatop_regs =
                (struct anatop_regs *)ANATOP_BASE_ADDR;
        struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+       u32 lvds1_clk_sel;
 
        /*
         * Here be dragons!
@@ -608,17 +609,25 @@ int enable_pcie_clock(void)
         * marked as ANATOP_MISC1 is actually documented in the PMU section
         * of the datasheet as PMU_MISC1.
         *
-        * Switch LVDS clock source to SATA (0xb), disable clock INPUT and
-        * enable clock OUTPUT. This is important for PCI express link that
-        * is clocked from the i.MX6.
+        * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
+        * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
+        * for PCI express link that is clocked from the i.MX6.
         */
 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN         (1 << 12)
 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN         (1 << 10)
 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK    0x0000001F
+#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF        0xa
+#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF        0xb
+
+       if (is_cpu_type(MXC_CPU_MX6SX))
+               lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
+       else
+               lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
+
        clrsetbits_le32(&anatop_regs->ana_misc1,
                        ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
                        ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
-                       ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);
+                       ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
 
        /* PCIe reference clock sourced from AXI. */
        clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);

diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h
index f54db6944dddd9b62ad0b6bcfd791d8dda3db53c..9b3a91f0766e88ef9a878872d39784063ccb2bea 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/iomux.h
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@@ -18,6 +18,12 @@
 #define IOMUXC_GPR1_REF_SSP_EN                 (1 << 16)
 #define IOMUXC_GPR1_TEST_POWERDOWN             (1 << 18)
 
+/*
+ * IOMUXC_GPR5 bit fields
+ */
+#define IOMUXC_GPR5_PCIE_BTNRST                        (1 << 19)
+#define IOMUXC_GPR5_PCIE_PERST                 (1 << 18)
+
 /*
  * IOMUXC_GPR8 bit fields
  */
@@ -35,12 +41,15 @@
 /*
  * IOMUXC_GPR12 bit fields
  */
+#define IOMUXC_GPR12_RX_EQ_2                   (0x2 << 0)
+#define IOMUXC_GPR12_RX_EQ_MASK                        (0x7 << 0)
 #define IOMUXC_GPR12_LOS_LEVEL_9               (0x9 << 4)
 #define IOMUXC_GPR12_LOS_LEVEL_MASK            (0x1f << 4)
 #define IOMUXC_GPR12_APPS_LTSSM_ENABLE         (1 << 10)
 #define IOMUXC_GPR12_DEVICE_TYPE_EP            (0x0 << 12)
 #define IOMUXC_GPR12_DEVICE_TYPE_RC            (0x4 << 12)
 #define IOMUXC_GPR12_DEVICE_TYPE_MASK          (0xf << 12)
+#define IOMUXC_GPR12_TEST_POWERDOWN            (1 << 30)
 
 /*
  * IOMUXC_GPR13 bit fields

diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index a3982c4553e0e5f8ff23bf3be942a44cffffb969..fd7e4d499f06b01fa8bd5a491b7eaaccff0943d3 100644 (file)
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -23,13 +23,20 @@
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
 
+#ifdef CONFIG_MX6SX
+#define MX6_DBI_ADDR   0x08ffc000
+#define MX6_IO_ADDR    0x08000000
+#define MX6_MEM_ADDR   0x08100000
+#define MX6_ROOT_ADDR  0x08f00000
+#else
 #define MX6_DBI_ADDR   0x01ffc000
-#define MX6_DBI_SIZE   0x4000
 #define MX6_IO_ADDR    0x01000000
-#define MX6_IO_SIZE    0x100000
 #define MX6_MEM_ADDR   0x01100000
-#define MX6_MEM_SIZE   0xe00000
 #define MX6_ROOT_ADDR  0x01f00000
+#endif
+#define MX6_DBI_SIZE   0x4000
+#define MX6_IO_SIZE    0x100000
+#define MX6_MEM_SIZE   0xe00000
 #define MX6_ROOT_SIZE  0xfc000
 
 /* PCIe Port Logic registers (memory-mapped) */
@@ -57,6 +64,8 @@
 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
 
+#define PCIE_PHY_PUP_REQ               (1 << 7)
+
 /* iATU registers */
 #define PCIE_ATU_VIEWPORT              0x900
 #define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
@@ -421,9 +430,19 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
 static int imx6_pcie_assert_core_reset(void)
 {
        struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
+#if defined(CONFIG_MX6SX)
+       struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
+
+       /* SSP_EN is not used on MX6SX anymore */
+       setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
+       /* Force PCIe PHY reset */
+       setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
+       /* Power up PCIe PHY */
+       setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
+#else
        setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
        clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+#endif
 
        return 0;
 }
@@ -441,6 +460,12 @@ static int imx6_pcie_init_phy(void)
                        IOMUXC_GPR12_LOS_LEVEL_MASK,
                        IOMUXC_GPR12_LOS_LEVEL_9);
 
+#ifdef CONFIG_MX6SX
+       clrsetbits_le32(&iomuxc_regs->gpr[12],
+                       IOMUXC_GPR12_RX_EQ_MASK,
+                       IOMUXC_GPR12_RX_EQ_2);
+#endif
+
        writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
               (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
               (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
@@ -517,9 +542,16 @@ static int imx6_pcie_deassert_core_reset(void)
         */
        mdelay(50);
 
+#if defined(CONFIG_MX6SX)
+       /* SSP_EN is not used on MX6SX anymore */
+       clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
+       /* Clear PCIe PHY reset bit */
+       clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
+#else
        /* Enable PCIe */
        clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
        setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+#endif
 
        imx6_pcie_toggle_reset();