]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
clk: set flags in the ccf registration routines
authorDario Binacchi <dariobin@libero.it>
Mon, 13 Apr 2020 12:36:27 +0000 (14:36 +0200)
committerLukasz Majewski <lukma@denx.de>
Mon, 24 Aug 2020 09:03:26 +0000 (11:03 +0200)
The top-level framework flags are passed as parameter to the common
clock framework (ccf) registration routines without being used.
Checks of the flags setting added by the patch have been added in the
ccf test.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
drivers/clk/clk-composite.c
drivers/clk/clk-divider.c
drivers/clk/clk-fixed-factor.c
drivers/clk/clk-gate.c
drivers/clk/clk-mux.c
drivers/clk/clk_sandbox_ccf.c
test/dm/clk_ccf.c

index 819bfca2fcf9d7a6f37700d213cee5bbbb1b7ff1..7e99c5b910da06abb7925a789cd544ae9d954c77 100644 (file)
@@ -145,6 +145,7 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
        }
 
        clk = &composite->clk;
+       clk->flags = flags;
        ret = clk_register(clk, UBOOT_DM_CLK_COMPOSITE, name,
                           parent_names[clk_composite_get_parent(clk)]);
        if (ret) {
index 34658536c48380f4892c993faab0727dcb5a80f5..8f59d7fb72c9ec1f5c5493381c711a4c18d4bd8a 100644 (file)
@@ -212,6 +212,7 @@ static struct clk *_register_divider(struct device *dev, const char *name,
 
        /* register the clock */
        clk = &div->clk;
+       clk->flags = flags;
 
        ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, parent_name);
        if (ret) {
index 0eb24b87fc39435795bad51eb582930d994baee0..8d9823bdab9328c10dedfc932e2a35f30e3e7e55 100644 (file)
@@ -49,6 +49,7 @@ struct clk *clk_hw_register_fixed_factor(struct device *dev,
        fix->mult = mult;
        fix->div = div;
        clk = &fix->clk;
+       clk->flags = flags;
 
        ret = clk_register(clk, UBOOT_DM_CLK_IMX_FIXED_FACTOR, name,
                           parent_name);
index 98e4b80b32f9b94b91d57a9dc642f61913626f1a..006d3b6629c0bb3c73689eec2aff2b7810711386 100644 (file)
@@ -142,6 +142,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
 #endif
 
        clk = &gate->clk;
+       clk->flags = flags;
 
        ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name);
        if (ret) {
index 26991a5bc8fcadae3b714c0cc7f86aa26bae0469..679d66a85b8b45ee7837a5e87f944cc8491ddb10 100644 (file)
@@ -185,6 +185,7 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
 #endif
 
        clk = &mux->clk;
+       clk->flags = flags;
 
        /*
         * Read the current mux setup - so we assign correct parent.
index e90b860257f64df5d2f30d37b1d70dc69426b063..fedcdd40448bb9ebc2aaae279d66c3c88a1d01e3 100644 (file)
@@ -130,6 +130,7 @@ struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
 
        gate->state = 0;
        clk = &gate->clk;
+       clk->flags = flags;
 
        ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name);
        if (ret) {
@@ -272,7 +273,7 @@ static int sandbox_clk_ccf_probe(struct udevice *dev)
        reg = BIT(28) | BIT(24) | BIT(16);
        clk_dm(SANDBOX_CLK_I2C,
               sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels),
-                                    &reg, 0));
+                                    &reg, CLK_SET_RATE_UNGATE));
 
        clk_dm(SANDBOX_CLK_I2C_ROOT,
               sandbox_clk_gate2("i2c_root", "i2c", base + 0x7c, 0));
index 960cb2db0d49f34ec871a2aacdbaa541b92f67e6..242d2d756fd75fd9a3127b9fec294d2d560531a1 100644 (file)
@@ -30,11 +30,13 @@ static int dm_test_clk_ccf(struct unit_test_state *uts)
        ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk);
        ut_assertok(ret);
        ut_asserteq_str("ecspi_root", clk->dev->name);
+       ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);
 
        /* Test for clk_get_parent_rate() */
        ret = clk_get_by_id(SANDBOX_CLK_ECSPI1, &clk);
        ut_assertok(ret);
        ut_asserteq_str("ecspi1", clk->dev->name);
+       ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);
 
        rate = clk_get_parent_rate(clk);
        ut_asserteq(rate, 20000000);
@@ -43,6 +45,7 @@ static int dm_test_clk_ccf(struct unit_test_state *uts)
        ret = clk_get_by_id(SANDBOX_CLK_ECSPI0, &clk);
        ut_assertok(ret);
        ut_asserteq_str("ecspi0", clk->dev->name);
+       ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);
 
        rate = clk_get_parent_rate(clk);
        ut_asserteq(rate, 20000000);
@@ -51,6 +54,7 @@ static int dm_test_clk_ccf(struct unit_test_state *uts)
        ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
        ut_assertok(ret);
        ut_asserteq_str("usdhc1_sel", clk->dev->name);
+       ut_asserteq(CLK_SET_RATE_NO_REPARENT, clk->flags);
 
        rate = clk_get_parent_rate(clk);
        ut_asserteq(rate, 60000000);
@@ -58,17 +62,20 @@ static int dm_test_clk_ccf(struct unit_test_state *uts)
        ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk);
        ut_assertok(ret);
        ut_asserteq_str("usdhc2_sel", clk->dev->name);
+       ut_asserteq(CLK_SET_RATE_NO_REPARENT, clk->flags);
 
        rate = clk_get_parent_rate(clk);
        ut_asserteq(rate, 80000000);
 
        pclk = clk_get_parent(clk);
        ut_asserteq_str("pll3_80m", pclk->dev->name);
+       ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags);
 
        /* Test the composite of CCF */
        ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk);
        ut_assertok(ret);
        ut_asserteq_str("i2c", clk->dev->name);
+       ut_asserteq(CLK_SET_RATE_UNGATE, clk->flags);
 
        rate = clk_get_rate(clk);
        ut_asserteq(rate, 60000000);