ARM: dts: am43xx-clocks: add spread spectrum support

Registers for adjusting the spread spectrum clocking (SSC) have been
added. As reported by the TI spruhl7x RM, SSC is supported only for LCD
and MPU PLLs, but the PRCM_CM_SSC_DELTAMSTEP_DPLL_XXX and
PRCM_CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field
in the PRCM_CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE,
MPU, DDR, PER, DISP, EXTDEV).

Link: https://lore.kernel.org/r/20210606202253.31649-5-dariobin@libero.it
Signed-off-by: Dario Binacchi <dariobin@libero.it>

diff --git a/arch/arm/dts/am43xx-clocks.dtsi b/arch/arm/dts/am43xx-clocks.dtsi
index d0c0dfa4ec486e5927abda3d9f4189435a51d23e..b1127b5b91fe6ae30c044cf1357b7a2f98977e6e 100644 (file)
--- a/arch/arm/dts/am43xx-clocks.dtsi
+++ b/arch/arm/dts/am43xx-clocks.dtsi
@@ -199,7 +199,7 @@
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-core-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x2d20>, <0x2d24>, <0x2d2c>;
+               reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>;
        };
 
        dpll_core_x2_ck: dpll_core_x2_ck {
@@ -245,7 +245,7 @@
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x2d60>, <0x2d64>, <0x2d6c>;
+               reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>;
        };
 
        dpll_mpu_m2_ck: dpll_mpu_m2_ck {
@@ -263,7 +263,7 @@
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x2da0>, <0x2da4>, <0x2dac>;
+               reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>;
        };
 
        dpll_ddr_m2_ck: dpll_ddr_m2_ck {
@@ -281,7 +281,7 @@
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x2e20>, <0x2e24>, <0x2e2c>;
+               reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>;
        };
 
        dpll_disp_m2_ck: dpll_disp_m2_ck {
@@ -300,7 +300,7 @@
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-j-type-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x2de0>, <0x2de4>, <0x2dec>;
+               reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>;
        };
 
        dpll_per_m2_ck: dpll_per_m2_ck {
@@ -583,7 +583,7 @@
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x2e60>, <0x2e64>, <0x2e6c>;
+               reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>;
        };
 
        dpll_extdev_m2_ck: dpll_extdev_m2_ck {