drivers: ddr: Remove duplicate newlines

Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
index bd2af94bb0dd014a4830ceb6b688374777bb2d46..d3305a6c82dfabd6aff95c7c263eb132c24c9315 100644 (file)
--- a/drivers/ddr/altera/sdram_arria10.c
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -645,7 +645,6 @@ static int of_sdram_firewall_setup(const void *blob)
        writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
        writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
 
-
        for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
                sprintf(name, "%s", firewall_table[i].prop_name);
                ret = fdtdec_get_int_array(blob, child, name,

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 7636e71a0a6b69e302d5819ce5e78ec5f682f4aa..69937fc2d5664bf8aa5a1fe2d59ada91986308fb 100644 (file)
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -689,7 +689,6 @@ static void scc_mgr_apply_group_dm_out1_delay(struct socfpga_sdrseq *seq,
        }
 }
 
-
 /* apply and load delay on both DQS and OCT out1 */
 static void scc_mgr_apply_group_dqs_io_and_oct_out1(struct socfpga_sdrseq *seq,
                                                    u32 write_group, u32 delay)
@@ -2580,7 +2579,6 @@ static int rw_mgr_mem_calibrate_vfifo_center(struct socfpga_sdrseq *seq,
                         &sticky_bit_chk,
                         left_edge, right_edge, use_read_test);
 
-
        /* Search for the right edge of the window for each bit */
        ret = search_right_edge(seq, 0, rank_bgn, rw_group, rw_group,
                                start_dqs, start_dqs_en,

diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index 618ba00da645d6d008d5f72f5d6e7682b7d94032..96a6bac83b44d38745d131f219a4d588c6563b8d 100644 (file)
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -164,7 +164,6 @@ struct param_type {
        u32     write_correct_mask_vg;
 };
 
-
 /* global variable holder */
 struct gbl_type {
        uint32_t phy_debug_mode_flags;

diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index 9f9aea804d97a2753c04a7e319f18c0793974225..f1dcba4603e108cf0699e93d62d94010287fc713 100644 (file)
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -19,7 +19,6 @@
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
 #endif
 
-
 /*
  * regs has the to-be-set values for DDR controller registers
  * ctrl_num is the DDR controller number

diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index 94a5e447d56ac4b5c013d48ab8b8695cebb7801f..52a20504bd9abab9871a7d6e9e37acd83b31484e 100644 (file)
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -1209,7 +1209,6 @@ void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
        for (i = 0; i < 18; i++)
                printf("%c", spd->mpart[i]);
 
-
        printf("<<* 73 Manufacturer's Part Number *\n");
 
        printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
@@ -1227,7 +1226,6 @@ void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
        for (i = 0; i < 27; i++)
                printf("%02x", spd->mspec[i]);
 
-
        printf("* 99 Manufacturer Specific Data *\n");
 }
 #endif
@@ -1946,7 +1944,6 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
                if (argc == 0)
                        continue;
 
-
                if (strcmp(argv[0], "help") == 0) {
                        puts(usage);
                        continue;
@@ -2042,7 +2039,6 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
                        debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
                                src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
 
-
                        switch (step_mask) {
 
                        case STEP_GET_SPD:
@@ -2117,7 +2113,6 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
                        if (error)
                                continue;
 
-
                        /* Check arguments */
 
                        /* ERROR: If no steps were found */

diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c
index aaf9800b3723276afff5fc36ab5cde97d7742688..cc128112e4fc752c90443dad9fb08aa64c80b266 100644 (file)
--- a/drivers/ddr/fsl/lc_common_dimm_params.c
+++ b/drivers/ddr/fsl/lc_common_dimm_params.c
@@ -191,7 +191,6 @@ compute_cas_latency(const unsigned int ctrl_num,
              lowest_good_caslat);
        outpdimm->lowest_common_spd_caslat = lowest_good_caslat;
 
-
        /*
         * Compute a common 'de-rated' CAS latency.
         *

diff --git a/drivers/ddr/imx/phy/ddrphy_train.c b/drivers/ddr/imx/phy/ddrphy_train.c
index ccc10df1845282e5b1e1ac25eaa106dd09f7bbc2..2a2161dec335b05d63baad91bd2f63f68773cd61 100644 (file)
--- a/drivers/ddr/imx/phy/ddrphy_train.c
+++ b/drivers/ddr/imx/phy/ddrphy_train.c
@@ -78,7 +78,6 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing)
 
                dwc_ddrphy_apb_wr(0xd0000, 0x1);
 
-
                fsp_msg++;
        }
 

diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c
index 7c5147f4745759455ba92f6022cb41e82ebfb7b8..b28b2c73a8bd6b9e2f372c9fbc2bf88383278b2b 100644 (file)
--- a/drivers/ddr/marvell/a38x/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/ddr3_init.c
@@ -75,7 +75,6 @@ int ddr3_init(void)
 #endif
        }
 
-
        status = ddr3_silicon_post_init();
        if (MV_OK != status) {
                printf("DDR3 Post Init - FAILED 0x%x\n", status);
@@ -89,7 +88,6 @@ int ddr3_init(void)
                return status;
        }
 
-
        /* Post MC/PHY initializations */
        mv_ddr_post_training_soc_config(ddr_type);
 

diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c
index 790b01d031d12e11a60081f169d44ee013231f44..5b8747cc681f87147747dad56d90d382cb779620 100644 (file)
--- a/drivers/ddr/marvell/a38x/ddr3_training.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -285,7 +285,6 @@ int ddr3_tip_tune_training_params(u32 dev_num,
        if (params->g_rtt_park != PARAM_UNDEFINED)
                g_rtt_park = params->g_rtt_park;
 
-
        DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
                          ("DGL parameters: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n",
                           g_zpri_data, g_znri_data, g_zpri_ctrl, g_znri_ctrl, g_zpodt_data, g_znodt_data,
@@ -870,7 +869,6 @@ int ddr3_tip_validate_algo_components(u8 dev_num)
        return (status == 1) ? MV_OK : MV_NOT_INITIALIZED;
 }
 
-
 int ddr3_pre_algo_config(void)
 {
        struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
@@ -1114,7 +1112,6 @@ int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type interface_access,
                mv_ddr_phy_write(phy_access, phy_id, phy_type, reg_addr, data_value, OPERATION_WRITE);
 }
 
-
 /*
  * Phy read-modify-write
  */
@@ -1406,7 +1403,6 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
                        t2t = (cs_num == 1) ? 0 : 1;
                }
 
-
                if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_INTERLEAVE_WA) == 1) {
                        /* Use 1T mode if 1:1 ratio configured */
                        if (config_func_info[dev_num].tip_get_clock_ratio(frequency) == 1) {

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
index 8765df7cfbb4284c7418c6663a1241961ea3e0ff..bdd7836b8441073d2a2a0406687ea51d1d88fb0c 100644 (file)
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
@@ -82,7 +82,6 @@
 #define ADDR_SIZE_8GB                  0x40000000
 #define ADDR_SIZE_16GB                 0x80000000
 
-
 enum hws_edge_compare {
        EDGE_PF,
        EDGE_FP,

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c
index 55abbad5a7a26881ae2410458d47e201983ac22f..bc58f55170c5323d9f29011490d5bfe09f07b256 100644 (file)
--- a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c
@@ -1677,7 +1677,6 @@ static int mpr_rd_frmt_config(
        u32 val, mask;
        u8 cs_bitmask_inv;
 
-
        if (dis_auto_refresh == 1) {
                ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_CTRL_CTRL_REG,
                          ODPG_CTRL_AUTO_REFRESH_DIS << ODPG_CTRL_AUTO_REFRESH_OFFS,

diff --git a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
index dff56338b19e500f38137f7be06203f0316c18b4..e6b7cc5985e47f8845f564130cad21d93ebb6ada 100644 (file)
--- a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
+++ b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
@@ -79,7 +79,6 @@
 #define MV_DEBUG_WL_FULL
 #endif
 
-
 /* The following is a list of Marvell status */
 #define MV_ERROR       (-1)
 #define MV_OK          (0x00)  /* Operation succeeded                   */

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
index 8ec9fb0874ea328303e920db6668d699fca3da3b..fb69539ef4c3179b60b2e9dd11cbf1c41cb60c7f 100644 (file)
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
@@ -1144,7 +1144,6 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
        uint64_t cs_mem_size = 0;
        uint64_t mem_total_size_c, cs_mem_size_c;
 
-
 #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
        u32 physical_mem_size;
        u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.h b/drivers/ddr/marvell/a38x/mv_ddr_plat.h
index 01894f652cb42d1160105a96edb8054b668e3a67..23f3dd628773feb59bfa76ba60199d8eb7e5a882 100644 (file)
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.h
@@ -55,7 +55,6 @@
 
 #define MARVELL_BOARD                          MARVELL_BOARD_ID_BASE
 
-
 #define REG_DEVICE_SAR1_ADDR                   0xe4204
 #define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET    17
 #define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK      0x1f

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_regs.h b/drivers/ddr/marvell/a38x/mv_ddr_regs.h
index a19000dbdd8a9babf3daa907e9e3fba78bcd4c05..6a8a921e534fbcff8ca2937785d221986da8fdea 100644 (file)
--- a/drivers/ddr/marvell/a38x/mv_ddr_regs.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_regs.h
@@ -520,5 +520,4 @@ enum {
 #define RESULT_PHY_RX_OFFS                     5
 #define RESULT_PHY_TX_OFFS                     0
 
-
 #endif /* _MV_DDR_REGS_H */