select SUPPORT_OF_CONTROL
select OF_CONTROL
select DM
- select SPL_SEPARATE_BSS if SPL
+ imply SPL_SEPARATE_BSS if SPL
imply DM_SERIAL
- imply DM_ETH
imply DM_EVENT
imply DM_MMC
imply DM_SPI
CONFIG_DRAM_ODT_EN=y
CONFIG_I2C0_ENABLE=y
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
- CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
+# CONFIG_NET is not set
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
# CONFIG_RAM_ROCKCHIP_DEBUG is not set
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_DM_RESET=y
+ CONFIG_DM_RNG=y
+ CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
- omap_nand_info[cs].control = NULL;
- omap_nand_info[cs].cs = cs;
- omap_nand_info[cs].ws = wscfg[cs];
+
+ info = &omap_nand_info[cs];
+ info->control = NULL;
+ info->cs = cs;
+ info->ws = wscfg[cs];
- info->fifo = (void __iomem *)CONFIG_SYS_NAND_BASE;
++ info->fifo = (void __iomem *)CFG_SYS_NAND_BASE;
nand_set_controller_data(nand, &omap_nand_info[cs]);
nand->cmd_ctrl = omap_nand_hwcontrol;
nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
/* RAW SD card / eMMC locations. */
/* FAT sd card locations. */
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xf8000000
+ #define ROCKPI_4B_IDBLOADER_IMAGE_GUID \
+ EFI_GUID(0x02f4d760, 0xcfd5, 0x43bd, 0x8e, 0x2d, \
+ 0xa4, 0x2a, 0xcb, 0x33, 0xc6, 0x60)
+
+ #define ROCKPI_4B_UBOOT_IMAGE_GUID \
+ EFI_GUID(0x4ce292da, 0x1dd8, 0x428d, 0xa1, 0xc2, \
+ 0x77, 0x74, 0x3e, 0xf8, 0xb9, 0x6e)
+
+ #define ROCKPI_4C_IDBLOADER_IMAGE_GUID \
+ EFI_GUID(0xfd68510c, 0x12d3, 0x4f0a, 0xb8, 0xd3, \
+ 0xd8, 0x79, 0xe1, 0xd3, 0xa5, 0x40)
+
+ #define ROCKPI_4C_UBOOT_IMAGE_GUID \
+ EFI_GUID(0xb81fb4ae, 0xe4f3, 0x471b, 0x99, 0xb4, \
+ 0x0b, 0x3d, 0xa5, 0x49, 0xce, 0x13)
+
#ifndef CONFIG_SPL_BUILD
#define ENV_MEM_LAYOUT_SETTINGS \
* is known yet.
* H6 has SRAM A1 at 0x00020000.
*/
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS
+#define CFG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS
/* FIXME: this may be larger on some SoCs */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
+#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
-#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_0 CFG_SYS_SDRAM_BASE
#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
- /* mmc config */
- #define CONFIG_MMC_SUNXI_SLOT 0
-#ifdef CONFIG_NAND_SUNXI
-#define CONFIG_SYS_NAND_MAX_ECCPOS 1664
-#endif
--
/*
* Miscellaneous configurable options
*/
CONFIG_MIU_2BIT_21_7_INTERLEAVED
CONFIG_MIU_2BIT_INTERLEAVED
CONFIG_MMC_DEFAULT_DEV
- CONFIG_MMC_SUNXI_SLOT
CONFIG_MONITOR_IS_IN_RAM
-CONFIG_MPC85XX_FEC
-CONFIG_MPC85XX_FEC_NAME
CONFIG_MTD_NAND_VERIFY_WRITE
-CONFIG_MTD_PARTITION
CONFIG_MVGBE_PORTS
-CONFIG_MVS
-CONFIG_MX27
-CONFIG_MX27_CLK32
CONFIG_MXC_GPT_HCLK
CONFIG_MXC_NAND_HWECC
CONFIG_MXC_NAND_IP_REGS_BASE