Add DDR3 support for AM335x-EVM (Version 1.5A)

AM335x EVM 1.5A uses Micron MT41J512M8RH-125 SDRAM 4Gb (512Mx8) as the
DDR3 chip.

[Hebbar Gururaja <gururaja.hebbar@ti.com>]
	- Resolve merge conflict while rebasing. File structure is
	  changed in the mainline. So re-arrange the code accordingly.
	- Update commit message to reflect the DDR3 part number

Signed-off-by: Jeff Lance <j-lance1@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>

diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index f95b332133ebf540b8a9c9e54521b63a599d15b5..ae43ef8778580aba42f8784d6eaa55e35be2073a 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -82,6 +82,22 @@
 #define MT41J256M8HX15E_PHY_FIFO_WE            0x100
 #define MT41J256M8HX15E_IOCTRL_VALUE           0x18B
 
+/* Micron MT41J512M8RH-125 on EVM v1.5 */
+#define MT41J512M8RH125_EMIF_READ_LATENCY      0x06
+#define MT41J512M8RH125_EMIF_TIM1              0x0888A39B
+#define MT41J512M8RH125_EMIF_TIM2              0x26517FDA
+#define MT41J512M8RH125_EMIF_TIM3              0x501F84EF
+#define MT41J512M8RH125_EMIF_SDCFG             0x61C04BB2
+#define MT41J512M8RH125_EMIF_SDREF             0x0000093B
+#define MT41J512M8RH125_ZQ_CFG                 0x50074BE4
+#define MT41J512M8RH125_DLL_LOCK_DIFF          0x1
+#define MT41J512M8RH125_RATIO                  0x80
+#define MT41J512M8RH125_INVERT_CLKOUT          0x0
+#define MT41J512M8RH125_RD_DQS                 0x3B
+#define MT41J512M8RH125_WR_DQS                 0x3C
+#define MT41J512M8RH125_PHY_FIFO_WE            0xA5
+#define MT41J512M8RH125_PHY_WR_DATA            0x74
+#define MT41J512M8RH125_IOCTRL_VALUE           0x18B
 
 /**
  * Configure SDRAM

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 7332601cbc78a56a482a0072d676cc29db040652..b9ac1d5982dd2dd6b93a1d600fd6d19f302f06b1 100644 (file)
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -73,6 +73,12 @@ static inline int board_is_idk(void)
        return !strncmp(header.config, "SKU#02", 6);
 }
 
+int board_is_evm_15_or_later(void)
+{
+       return (!strncmp("A33515BB", header.name, 8) &&
+               strncmp("1.5", header.version, 3) <= 0);
+}
+
 /*
  * Read header information from EEPROM into global structure.
  */
@@ -197,6 +203,14 @@ static const struct ddr_data ddr3_data = {
        .datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
+static const struct ddr_data ddr3_evm_data = {
+       .datardsratio0 = MT41J512M8RH125_RD_DQS,
+       .datawdsratio0 = MT41J512M8RH125_WR_DQS,
+       .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
+       .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
+       .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
 static const struct cmd_control ddr3_cmd_ctrl_data = {
        .cmd0csratio = MT41J128MJT125_RATIO,
        .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
@@ -211,6 +225,20 @@ static const struct cmd_control ddr3_cmd_ctrl_data = {
        .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 };
 
+static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
+       .cmd0csratio = MT41J512M8RH125_RATIO,
+       .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
+       .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+
+       .cmd1csratio = MT41J512M8RH125_RATIO,
+       .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
+       .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+
+       .cmd2csratio = MT41J512M8RH125_RATIO,
+       .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
+       .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+};
+
 static struct emif_regs ddr3_emif_reg_data = {
        .sdram_config = MT41J128MJT125_EMIF_SDCFG,
        .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
@@ -220,6 +248,16 @@ static struct emif_regs ddr3_emif_reg_data = {
        .zq_config = MT41J128MJT125_ZQ_CFG,
        .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
 };
+
+static struct emif_regs ddr3_evm_emif_reg_data = {
+       .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
+       .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
+       .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
+       .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
+       .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
+       .zq_config = MT41J512M8RH125_ZQ_CFG,
+       .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY,
+};
 #endif
 
 /*
@@ -301,6 +339,9 @@ void s_init(void)
        if (board_is_evm_sk() || board_is_bone_lt())
                config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
                           &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
+       else if (board_is_evm_15_or_later())
+               config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
+                          &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data);
        else
                config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
                           &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);