mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASE

CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as
CONFIG_SYS_SDRAM_BASE on all existing boards. Just use
CONFIG_SYS_SDRAM_BASE instead.

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index b3cbf9f88233ea5a8d7ee5efeabaecf489cbd5a1..5ca307ca583bfc3241b415b8fbef4db7fbc6bbe8 100644 (file)
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -281,7 +281,7 @@ long int spd_sdram()
        /*
         * Set up LAWBAR for all of DDR.
         */
-       ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+       ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
        ecm->ar  = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
        debug("DDR:bar=0x%08x\n", ecm->bar);
        debug("DDR:ar=0x%08x\n", ecm->ar);

diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c
index e64b3107b5ffd653005444b5663adf2b78118963..317e63ea6a14f32cae9634175613c99a006c1bba 100644 (file)
--- a/board/freescale/mpc8308rdb/sdram.c
+++ b/board/freescale/mpc8308rdb/sdram.c
@@ -33,7 +33,7 @@ static long fixed_sdram(void)
        u32 msize_log2 = __ilog2(msize);
 
        out_be32(&im->sysconf.ddrlaw[0].bar,
-                       CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
+                       CONFIG_SYS_SDRAM_BASE  & 0xfffff000);
        out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
        out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
 
@@ -61,7 +61,7 @@ static long fixed_sdram(void)
        setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
        sync();
 
-       return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+       return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
 }
 
 int dram_init(void)

diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index 5e074e3d87b3b348031164ea31021215813257f5..090412d4b6c942de5f249134eacb8997d9de0919 100644 (file)
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -47,7 +47,7 @@ static long fixed_sdram(void)
        volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
        u32 msize_log2 = __ilog2(msize);
 
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
        im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
        im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
 
@@ -57,12 +57,12 @@ static long fixed_sdram(void)
         */
        __udelay(50000);
 
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
 #warning Chip select bounds is only configurable in 16MB increments
 #endif
        im->ddr.csbnds[0].csbnds =
-               ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-               (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+               ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+               (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
                        CSBNDS_EA);
        im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 

diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c
index b9f94c83324d38eef822a747c64ccd11d7c6b1e3..2f0f29a0e57476b6c34158e3a1199793739aaf66 100644 (file)
--- a/board/freescale/mpc8315erdb/sdram.c
+++ b/board/freescale/mpc8315erdb/sdram.c
@@ -44,7 +44,7 @@ static long fixed_sdram(void)
        u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
        u32 msize_log2 = __ilog2(msize);
 
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE  & 0xfffff000;
        im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
        im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
 

diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index ea018e5d2013afe5c0a44f145b6d29d7e3733edd..f14276f6a876fbe283b384e231b4a0ed954665d5 100644 (file)
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -91,7 +91,7 @@ int fixed_sdram(void)
        u32 ddr_size = msize << 20;     /* DDR size in bytes */
        u32 ddr_size_log2 = __ilog2(ddr_size);
 
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
        im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 
 #if (CONFIG_SYS_DDR_SIZE != 256)
@@ -112,12 +112,12 @@ int fixed_sdram(void)
        im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 #else
 
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
 #warning Chip select bounds is only configurable in 16MB increments
 #endif
        im->ddr.csbnds[2].csbnds =
-               ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-               (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+               ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+               (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
                                CSBNDS_EA_SHIFT) & CSBNDS_EA);
        im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
 

diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index aaaea7ce89f84545090484d55cfdd12ec651fc75..81b3f00b56e8cfdb4e384cfe33a9cbd86733ffe2 100644 (file)
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -37,14 +37,14 @@ int fixed_sdram(void)
 
        im->sysconf.ddrlaw[0].ar =
            LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
 
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
 #warning Chip select bounds is only configurable in 16MB increments
 #endif
        im->ddr.csbnds[0].csbnds =
-               ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-               (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+               ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+               (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
                                CSBNDS_EA_SHIFT) & CSBNDS_EA);
        im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 

diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
index 09a046dff8d825c521e3d7e28b5df1c51bdd0863..16922087c01b4a79d7f0a20e886f478547042f1e 100644 (file)
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -252,7 +252,7 @@ int fixed_sdram(void)
        u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
        u32 msize_log2 = __ilog2(msize);
 
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
        im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 
 #if (CONFIG_SYS_DDR_SIZE != 512)

diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index d9a47b90b2f270c35222afbf7d9498835a44ad87..18f396aac8bd50009b9afaba7a0552eedfbfb55f 100644 (file)
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -95,7 +95,7 @@ int fixed_sdram(void)
        u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
        u32 msize_log2 = __ilog2(msize);
 
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
        im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 
        im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;

diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c
index 5ced8eb0819d23d1bbd6f4c94f6133c0afebb76b..3eb0e37b7b56944f8b1391ef5ae141ea9ead4614 100644 (file)
--- a/board/gdsys/mpc8308/sdram.c
+++ b/board/gdsys/mpc8308/sdram.c
@@ -34,7 +34,7 @@ static long fixed_sdram(void)
        u32 msize_log2 = __ilog2(msize);
 
        out_be32(&im->sysconf.ddrlaw[0].bar,
-                CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
+                CONFIG_SYS_SDRAM_BASE  & 0xfffff000);
        out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
        out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
 
@@ -62,7 +62,7 @@ static long fixed_sdram(void)
        setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
        sync();
 
-       return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+       return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
 }
 
 int dram_init(void)

diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c
index a37ca8a2f4417543ebcaf27c9b2b40b252b10aa9..a66234aa8578acf9d54848d53909236d8a442044 100644 (file)
--- a/board/ids/ids8313/ids8313.c
+++ b/board/ids/ids8313/ids8313.c
@@ -57,7 +57,7 @@ int fixed_sdram(unsigned long config)
        u32 msize_log2 = __ilog2(msize);
 
        out_be32(&im->sysconf.ddrlaw[0].bar,
-                (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+                (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
        out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
        out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
        sync();

diff --git a/board/mpc8308_p1m/sdram.c b/board/mpc8308_p1m/sdram.c
index 4118c019ccf91dafb9d1ddf2ff6c6a38b1245c29..baf70d8807b0b7265d4517c124397a46d583bb9d 100644 (file)
--- a/board/mpc8308_p1m/sdram.c
+++ b/board/mpc8308_p1m/sdram.c
@@ -29,7 +29,7 @@ static long fixed_sdram(void)
        u32 msize_log2 = __ilog2(msize);
 
        out_be32(&im->sysconf.ddrlaw[0].bar,
-                       CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
+                       CONFIG_SYS_SDRAM_BASE  & 0xfffff000);
        out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
        out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
 
@@ -57,7 +57,7 @@ static long fixed_sdram(void)
        setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
        sync();
 
-       return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+       return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
 }
 
 int dram_init(void)

diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 5584b3d17960770200bce33bf2f428e9f5c8a43b..e51eeae065dfe165b0be8985b13e4eb07c391549 100644 (file)
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -79,19 +79,19 @@ int fixed_sdram(void)
        u32 ddr_size = msize << 20;     /* DDR size in bytes */
        u32 ddr_size_log2 = __ilog2(msize);
 
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
        im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 
 #if (CONFIG_SYS_DDR_SIZE != 256)
 #warning Currently any ddr size other than 256 is not supported
 #endif
 
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
 #warning Chip select bounds is only configurable in 16MB increments
 #endif
        im->ddr.csbnds[2].csbnds =
-               ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-               (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+               ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+               (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
                                CSBNDS_EA_SHIFT) & CSBNDS_EA);
        im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
 

diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
index 609585bc653a749f18343773fb8a798be0fd9813..f4148a21e3b0778a9d5c8d2654b6268075aa02b7 100644 (file)
--- a/board/ve8313/ve8313.c
+++ b/board/ve8313/ve8313.c
@@ -38,7 +38,7 @@ static long fixed_sdram(void)
        u32 msize_log2 = __ilog2(msize);
 
        out_be32(&im->sysconf.ddrlaw[0].bar,
-               (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+               (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
        out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
        out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
 
@@ -48,12 +48,12 @@ static long fixed_sdram(void)
         */
        __udelay(50000);
 
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
 #warning Chip select bounds is only configurable in 16MB increments
 #endif
        out_be32(&im->ddr.csbnds[0].csbnds,
-               ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-               (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+               ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+               (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
                        CSBNDS_EA));
        out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
 

diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 6d018fde2b2fc7fecc501e8fb22948b715794d77..e1f69a1d25cc5168b40f8249a3083c66feb520f7 100644 (file)
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -23,8 +23,12 @@
  * 0x80_8000_0000 ~ 0xff_ffff_ffff
  */
 #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+#ifdef CONFIG_MPC83xx
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
+#else
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
 #endif
+#endif
 
 #ifdef CONFIG_PPC
 #include <asm/fsl_law.h>

diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index d9361fd8a03370d55e4fef67e13d5a83858759e2..5d31d4a0b6b6188d615c7d2f19bf22ab6c444454 100644 (file)
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -37,7 +37,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN \
                                | DDRCDR_PZ_LOZ \

diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h
index 08c83996c732253e7f68548382bb1f846b518704..6f100fc7e7bcd2edbbbe091362c9d6d5a7f1def1 100644 (file)
--- a/include/configs/MPC8313ERDB_NAND.h
+++ b/include/configs/MPC8313ERDB_NAND.h
@@ -87,7 +87,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 
 /*
  * Manually set up DDR parameters, as this board does not

diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h
index 169cc09d06b17e17d01162b05ab1a1289778338c..0f246dc5186587a249271829a91a50461cb87673 100644 (file)
--- a/include/configs/MPC8313ERDB_NOR.h
+++ b/include/configs/MPC8313ERDB_NOR.h
@@ -59,7 +59,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 
 /*
  * Manually set up DDR parameters, as this board does not

diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index c5a229deb4cd13b7b4e92b4d1f3325dbcd77c57a..0b94b0c5cf920ea28d15dc2e05b8ca8f12960c6d 100644 (file)
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -35,7 +35,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN \
                                | DDRCDR_PZ_LOZ \

diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 3e6febfc9d35b88a4ced7682ce0703f7389d0078..a90a9a86f8d62ebb6164590b9b75815ffdd4898a 100644 (file)
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -24,7 +24,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE  0x00000000      /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 
 #undef CONFIG_SPD_EEPROM
 #if defined(CONFIG_SPD_EEPROM)

diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 4b3f70c916cb34e7f273bf521e7cd0528b8cd6fa..88b6f87397801ad7783c00af828c5731168a492e 100644 (file)
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -21,7 +21,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE  0x00000000      /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDRCDR      0x73000002      /* DDR II voltage is 1.8V */
 
 #undef CONFIG_SPD_EEPROM

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 1a96be0895c130c7d6fa36ae301c33243daa7010..fdbd15ea93eb0e4a47cb32e708f03f9e1590a466 100644 (file)
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -53,7 +53,6 @@
 #undef CONFIG_DDR_32BIT
 
 #define CONFIG_SYS_SDRAM_BASE  0x00000000      /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN \
                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 #undef  CONFIG_DDR_2T_TIMING

diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
index 311f87b5b3c13873f1070787e41dfc1a4408affc..1e0e297351eefb1727efeeb12d213c76240247c5 100644 (file)
--- a/include/configs/MPC8349EMDS_SDRAM.h
+++ b/include/configs/MPC8349EMDS_SDRAM.h
@@ -53,7 +53,6 @@
 #undef CONFIG_DDR_32BIT
 
 #define CONFIG_SYS_SDRAM_BASE  0x00000000      /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN \
                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 #undef  CONFIG_DDR_2T_TIMING

diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index bb3bcfcc44800625ea0fd9127065b639dc92e30c..388910ac38d54982b37ecde6c4f031cc2f0e64f7 100644 (file)
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -143,7 +143,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 #define CONFIG_SYS_MEMTEST_START       0x1000  /* memtest region */
 #define CONFIG_SYS_MEMTEST_END         0x2000

diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index e34a36cadd884b37b64dc71ef7fc597b51a234a7..61f9eaf71505fadbb1e34d15eb8077a0f048e71e 100644 (file)
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -36,7 +36,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 #define CONFIG_SYS_DDRCDR_VALUE                (DDRCDR_DHC_EN \

diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 33d4ced92f79a633e19f836d8ba39df76961fd1e..07b206ff9f950efb07310945d2490078d53d4a5f 100644 (file)
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -59,7 +59,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  0x03000000
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 

diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 53fac4d675a8b129671d5b6ba072bc02b973d090..0da34d05afcb4d603f9dc6d8cf0f000e307740c1 100644 (file)
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -25,7 +25,6 @@
  */
                                /* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE  0x00000000
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define DDR_CASLAT_25          /* CASLAT set to 2.5 */
 #undef CONFIG_DDR_ECC          /* only for ECC DDR module */
 #undef CONFIG_SPD_EEPROM       /* do not use SPD EEPROM for DDR setup */

diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h
index f14e5faafa658a24ae58a5bce96db9c43b9ab66a..928136f325f666002b2446a8a279691198815003 100644 (file)
--- a/include/configs/caddy2.h
+++ b/include/configs/caddy2.h
@@ -52,7 +52,6 @@
 #undef CONFIG_DDR_32BIT
 
 #define CONFIG_SYS_SDRAM_BASE          0x00000000      /* DDR is sys memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN \
                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING

diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index ae3fcfd3d79a4ad90bf0c40de0e3477dc2e88632..d73e848b0c72c3238d101a36e0f91b84b5ef5a76 100644 (file)
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -25,7 +25,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN \
                                | DDRCDR_PZ_LOZ \

diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index 504a136daab23566098d8341b758f92ce2fcad21..155815a8815c5e8920be17a9d41bae679c679e5e 100644 (file)
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -52,7 +52,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 
 /*
  * Manually set up DDR parameters,

diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h
index 5c4df18ca64d2b4a8ca887666d2f5b9c82120970..847996f9a49f8c5567a5846514324281120f2a84 100644 (file)
--- a/include/configs/kmcoge5ne.h
+++ b/include/configs/kmcoge5ne.h
@@ -46,7 +46,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index 2e8affb618014dc63812d7234873cf7c5cda1099..290108d4fc44bfaef4a2157bc4794f3dbbdb01e7 100644 (file)
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -31,7 +31,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h
index 3be53285dbcfd4def19fbc74278fefb984e5602b..0759604810a613694c7dfe578cee01683a5b51c7 100644 (file)
--- a/include/configs/kmopti2.h
+++ b/include/configs/kmopti2.h
@@ -51,7 +51,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h
index 74e719cc79ff59feceb1603c6644b820e67ae83b..319e3bc1ece3bcbb2aa92f21111071bb17d4be8e 100644 (file)
--- a/include/configs/kmsupx5.h
+++ b/include/configs/kmsupx5.h
@@ -51,7 +51,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h
index c6913838ce79c0062224ef10866fba6cc1b4c747..85e9101b054bfca5fa501436c7d5452ca8bbe33f 100644 (file)
--- a/include/configs/kmtegr1.h
+++ b/include/configs/kmtegr1.h
@@ -58,7 +58,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h
index 4af86195c5e5e9e585978f6a5f96846bd9e47bfe..6ec944f9429c123949a3a7a90e59d94674fccb98 100644 (file)
--- a/include/configs/kmtepr2.h
+++ b/include/configs/kmtepr2.h
@@ -51,7 +51,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h
index d8f4d269ed401a32cdb429d7f7615b42d6599f71..d7cbdde215d3495d98f44a375f1446ef6158d69d 100644 (file)
--- a/include/configs/kmvect1.h
+++ b/include/configs/kmvect1.h
@@ -50,7 +50,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index 8836b70b762770a53f961847ca601c246a589a66..0392c3e8b40f21e284e78467c9471de5ed18d16f 100644 (file)
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -40,7 +40,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN \
                                | DDRCDR_PZ_LOZ \

diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 709387ecf7996e19309e73ba55e4b92ef975ef70..b4ae7b75543956a21b8f917153170e665c8ccdd7 100644 (file)
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -47,7 +47,6 @@
 #undef CONFIG_DDR_32BIT
 
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING

diff --git a/include/configs/strider.h b/include/configs/strider.h
index c01531c3ca235132c5dec47bc5b7bdd36d586c57..e92bd1e8f105da82f7712ac8da94e370794d8e1f 100644 (file)
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -25,7 +25,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN \
                                | DDRCDR_PZ_LOZ \

diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index 3521de8d2ee582157f5f2e6869c84b37df597395..8b3b45416daf29607e5dd3031f3c4c59bde69eac 100644 (file)
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -48,7 +48,6 @@
 #define CONFIG_SYS_SDRAM_BASE  0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h
index 86e402ae233c4690c0407b09449c39a99f6967fe..5dc9e8997e5af0730b704fcecc3109f08ac56ff2 100644 (file)
--- a/include/configs/tuge1.h
+++ b/include/configs/tuge1.h
@@ -51,7 +51,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h
index ec1ac399a0c09a6f456f7edcaf809094984a2c94..9f8c855fb81807ec3dda968e410e3a2710555d79 100644 (file)
--- a/include/configs/tuxx1.h
+++ b/include/configs/tuxx1.h
@@ -51,7 +51,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index cd6c686b890e30fdff77de2ace6a519b71d88330..2116d6bbcf8b8a4e3d84a2c592c1fa6e92728878 100644 (file)
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -35,7 +35,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 
 /*
  * Manually set up DDR parameters, as this board does not

diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 14a84fabc97e86f000512be5bc3da9e5189a073a..1bce6c732d99d1b3b67480caf7345dbb7eed63d7 100644 (file)
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -52,7 +52,6 @@
 #undef CONFIG_DDR_32BIT
 
 #define CONFIG_SYS_SDRAM_BASE          0x00000000      /* DDR is sys memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN \
                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING