arm: socfpga: soc64: Initialize timer in SPL only

Timer only need to be initialized once in SPL.
This patch remove the redundancy of initializing the
timer again in U-Boot proper

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>

diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c
index 3ad98bdb251d0c1f88498ae65f247711b3825c9c..7d5598e1a3a44fa82500026190f48239310bdcbf 100644 (file)
--- a/arch/arm/mach-socfpga/timer_s10.c
+++ b/arch/arm/mach-socfpga/timer_s10.c
@@ -14,6 +14,7 @@
  */
 int timer_init(void)
 {
+#ifdef CONFIG_SPL_BUILD
        int enable = 0x3;       /* timer enable + output signal masked */
        int loadval = ~0;
 
@@ -22,6 +23,6 @@ int timer_init(void)
        /* enable processor pysical counter */
        asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
        asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
-
+#endif
        return 0;
 }