ARM: imx: imx8mm: Add missing clock entries for FEC clock

All the FEC ethernet clock entries for iMX8MM are missing, while they
are already present on iMX8MQ. Fill in the nodes on iMX8MM, as the FEC
ethernet gets bogus clock information otherwise which makes ethernet
inoperable.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index c423ac0058d03f0739df792d59a6e6002d7c4e26..d123ba1625b6e1e63abe25b28dfe0bf9cf501bec 100644 (file)
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -578,3 +578,52 @@ u32 mxc_get_clock(enum mxc_clock clk)
 
        return 0;
 }
+
+#ifdef CONFIG_FEC_MXC
+int set_clk_enet(enum enet_freq type)
+{
+       u32 target;
+       u32 enet1_ref;
+
+       switch (type) {
+       case ENET_125MHZ:
+               enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+               break;
+       case ENET_50MHZ:
+               enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+               break;
+       case ENET_25MHZ:
+               enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       /* disable the clock first */
+       clock_enable(CCGR_ENET1, 0);
+       clock_enable(CCGR_SIM_ENET, 0);
+
+       /* set enet axi clock 266Mhz */
+       target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
+                CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+                CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+       clock_set_target_val(ENET_AXI_CLK_ROOT, target);
+
+       target = CLK_ROOT_ON | enet1_ref |
+                CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+                CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+       clock_set_target_val(ENET_REF_CLK_ROOT, target);
+
+       target = CLK_ROOT_ON |
+               ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+               CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+               CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+       clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
+
+       /* enable clock */
+       clock_enable(CCGR_SIM_ENET, 1);
+       clock_enable(CCGR_ENET1, 1);
+
+       return 0;
+}
+#endif

diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c
index 8b7a4dad65c9ace24b402454e4f8a8bb06756954..9e84e8d5b1886153170f892fac6a70320f5630b8 100644 (file)
--- a/arch/arm/mach-imx/imx8m/clock_slice.c
+++ b/arch/arm/mach-imx/imx8m/clock_slice.c
@@ -482,6 +482,16 @@ static struct clk_root_map root_array[] = {
          SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
          SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
        },
+       {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
+        {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
+         SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
+         AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
+       },
+       {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
+        {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+         SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+         AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+       },
        {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
         {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
          SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
@@ -509,6 +519,21 @@ static struct clk_root_map root_array[] = {
          SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
          SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
        },
+       {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
+        {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
+         SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+         AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
+       },
+       {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
+        {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
+         EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
+         VIDEO_PLL_CLK}
+       },
+       {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
+        {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
+         SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
+         AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+       },
        {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
         {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
          SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,