clk: exynos: Move pll code into clk-exynos7420

PLL utilities code is only used by clk-exynos7420 driver at the moment.
Move it into clk-exynos7420 to make clk-pll.c file available for CCF PLL
clocks implementation, which is coming in the next patches.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile
index c9f29c873e9b3b3689020cc2ddd666e54a2a5ade..7faf238571ef191cebe0590787161b8ea92d1fb4 100644 (file)
--- a/drivers/clk/exynos/Makefile
+++ b/drivers/clk/exynos/Makefile
@@ -3,5 +3,4 @@
 # Copyright (C) 2016 Samsung Electronics
 # Thomas Abraham <thomas.ab@samsung.com>
 
-obj-y                          += clk-pll.o
 obj-$(CONFIG_CLK_EXYNOS7420)   += clk-exynos7420.o

diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c
index 7d869eb02b8e429946d5cc68c975a241efd4dd4e..9caa932e12fb4657acfd9997bd3d84adc37f0afc 100644 (file)
--- a/drivers/clk/exynos/clk-exynos7420.c
+++ b/drivers/clk/exynos/clk-exynos7420.c
@@ -10,8 +10,15 @@
 #include <errno.h>
 #include <clk-uclass.h>
 #include <asm/io.h>
+#include <div64.h>
 #include <dt-bindings/clock/exynos7420-clk.h>
-#include "clk-pll.h"
+
+#define PLL145X_MDIV_SHIFT     16
+#define PLL145X_MDIV_MASK      0x3ff
+#define PLL145X_PDIV_SHIFT     8
+#define PLL145X_PDIV_MASK      0x3f
+#define PLL145X_SDIV_SHIFT     0
+#define PLL145X_SDIV_MASK      0x7
 
 #define DIVIDER(reg, shift, mask)      \
        (((readl(reg) >> shift) & mask) + 1)
@@ -64,6 +71,22 @@ struct exynos7420_clk_top0_priv {
        unsigned long sclk_uart2;
 };
 
+static unsigned long pll145x_get_rate(unsigned int *con1,
+                                     unsigned long fin_freq)
+{
+       unsigned long pll_con1 = readl(con1);
+       unsigned long mdiv, sdiv, pdiv;
+       u64 fvco = fin_freq;
+
+       mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
+       pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
+       sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
+
+       fvco *= mdiv;
+       do_div(fvco, (pdiv << sdiv));
+       return (unsigned long)fvco;
+}
+
 static ulong exynos7420_topc_get_rate(struct clk *clk)
 {
        struct exynos7420_clk_topc_priv *priv = dev_get_priv(clk->dev);

diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c
deleted file mode 100644 (file)
index 407fc71..0000000
--- a/drivers/clk/exynos/clk-pll.c
+++ /dev/null
@@ -1,32 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Exynos PLL helper functions for clock drivers.
- * Copyright (C) 2016 Samsung Electronics
- * Thomas Abraham <thomas.ab@samsung.com>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <div64.h>
-
-#define PLL145X_MDIV_SHIFT     16
-#define PLL145X_MDIV_MASK      0x3ff
-#define PLL145X_PDIV_SHIFT     8
-#define PLL145X_PDIV_MASK      0x3f
-#define PLL145X_SDIV_SHIFT     0
-#define PLL145X_SDIV_MASK      0x7
-
-unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq)
-{
-       unsigned long pll_con1 = readl(con1);
-       unsigned long mdiv, sdiv, pdiv;
-       uint64_t fvco = fin_freq;
-
-       mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
-       pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
-       sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
-
-       fvco *= mdiv;
-       do_div(fvco, (pdiv << sdiv));
-       return (unsigned long)fvco;
-}

diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h
deleted file mode 100644 (file)
index 7b7af5e..0000000
--- a/drivers/clk/exynos/clk-pll.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Exynos PLL helper functions for clock drivers.
- * Copyright (C) 2016 Samsung Electronics
- * Thomas Abraham <thomas.ab@samsung.com>
- */
-
-#ifndef __EXYNOS_CLK_PLL_H
-#define __EXYNOS_CLK_PLL_H
-
-unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
-
-#endif /* __EXYNOS_CLK_PLL_H */