Add LPDDR4 detection timings and support for RV1126.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
--- /dev/null
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xB,
+ .bk = 0x3,
+ .bw = 0x1,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x11,
+ .cs1_row = 0x11,
+ .cs0_high16bit_row = 0x0,
+ .cs1_high16bit_row = 0x0,
+ .ddrconfig = 0
+ },
+ {
+ {0x41241522},
+ {0x15050b07},
+ {0x00000602},
+ {0x00001111},
+ {0x00000054},
+ {0x00000000},
+ 0x000000ff
+ }
+ },
+ {
+ .ddr_freq = 1056, /* clock rate(MHz) */
+ .dramtype = LPDDR4,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 1
+ },
+ {
+ {
+ {0x00000000, 0x81081020}, /* MSTR */
+ {0x00000064, 0x00400094}, /* RFSHTMG */
+ {0x000000d0, 0x00030409}, /* INIT0 */
+ {0x000000d4, 0x00690000}, /* INIT1 */
+ {0x000000d8, 0x00000206}, /* INIT2 */
+ {0x000000dc, 0x0034001b}, /* INIT3 */
+ {0x000000e0, 0x00310000}, /* INIT4 */
+ {0x000000e8, 0x00110000}, /* INIT6 */
+ {0x000000ec, 0x00000000}, /* INIT7 */
+ {0x000000f4, 0x000f033f}, /* RANKCTL */
+ {0x00000100, 0x14161217}, /* DRAMTMG0 */
+ {0x00000104, 0x00040422}, /* DRAMTMG1 */
+ {0x00000108, 0x050a0e0f}, /* DRAMTMG2 */
+ {0x0000010c, 0x00808000}, /* DRAMTMG3 */
+ {0x00000110, 0x0a04060c}, /* DRAMTMG4 */
+ {0x00000114, 0x02040808}, /* DRAMTMG5 */
+ {0x00000118, 0x01010005}, /* DRAMTMG6 */
+ {0x0000011c, 0x00000401}, /* DRAMTMG7 */
+ {0x00000120, 0x00000606}, /* DRAMTMG8 */
+ {0x00000130, 0x00020000}, /* DRAMTMG12 */
+ {0x00000134, 0x0a100002}, /* DRAMTMG13 */
+ {0x00000138, 0x00000098}, /* DRAMTMG14 */
+ {0x00000180, 0x02100010}, /* ZQCTL0 */
+ {0x00000184, 0x01b00000}, /* ZQCTL1 */
+ {0x00000190, 0x07070001}, /* DFITMG0 */
+ {0x00000198, 0x07000101}, /* DFILPCFG0 */
+ {0x000001a0, 0xc0400003}, /* DFIUPD0 */
+ {0x00000240, 0x0b050d3c}, /* ODTCFG */
+ {0x00000244, 0x00000101}, /* ODTMAP */
+ {0x00000250, 0x00001f00}, /* SCHED */
+ {0x00000490, 0x00000001}, /* PCTRL_0 */
+ {0xffffffff, 0xffffffff}
+ }
+ },
+ {
+ {
+ {0x00000004, 0x0000008d}, /* PHYREG01 */
+ {0x00000014, 0x00000014}, /* PHYREG05 */
+ {0x00000018, 0x00000000}, /* PHYREG06 */
+ {0x0000001c, 0x0000000a}, /* PHYREG07 */
+ {0xffffffff, 0xffffffff}
+ }
+ }
+},
--- /dev/null
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xB,
+ .bk = 0x3,
+ .bw = 0x1,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x11,
+ .cs1_row = 0x11,
+ .cs0_high16bit_row = 0x0,
+ .cs1_high16bit_row = 0x0,
+ .ddrconfig = 0
+ },
+ {
+ {0x2f0d060a},
+ {0x07020804},
+ {0x00000602},
+ {0x00001111},
+ {0x00000054},
+ {0x00000000},
+ 0x000000ff
+ }
+ },
+ {
+ .ddr_freq = 328, /* clock rate(MHz) */
+ .dramtype = LPDDR4,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 0
+ },
+ {
+ {
+ {0x00000000, 0x81081020}, /* MSTR */
+ {0x00000064, 0x0014002e}, /* RFSHTMG */
+ {0x000000d0, 0x00020142}, /* INIT0 */
+ {0x000000d4, 0x00220000}, /* INIT1 */
+ {0x000000d8, 0x00000202}, /* INIT2 */
+ {0x000000dc, 0x00240012}, /* INIT3 */
+ {0x000000e0, 0x00310000}, /* INIT4 */
+ {0x000000e8, 0x00100000}, /* INIT6 */
+ {0x000000ec, 0x00000000}, /* INIT7 */
+ {0x000000f4, 0x000f033f}, /* RANKCTL */
+ {0x00000100, 0x0c070507}, /* DRAMTMG0 */
+ {0x00000104, 0x0003040b}, /* DRAMTMG1 */
+ {0x00000108, 0x04070c0d}, /* DRAMTMG2 */
+ {0x0000010c, 0x00505000}, /* DRAMTMG3 */
+ {0x00000110, 0x03040204}, /* DRAMTMG4 */
+ {0x00000114, 0x02030303}, /* DRAMTMG5 */
+ {0x00000118, 0x01010004}, /* DRAMTMG6 */
+ {0x0000011c, 0x00000301}, /* DRAMTMG7 */
+ {0x00000120, 0x00000303}, /* DRAMTMG8 */
+ {0x00000130, 0x00020000}, /* DRAMTMG12 */
+ {0x00000134, 0x00100002}, /* DRAMTMG13 */
+ {0x00000138, 0x00000030}, /* DRAMTMG14 */
+ {0x00000180, 0x00a40005}, /* ZQCTL0 */
+ {0x00000184, 0x00900000}, /* ZQCTL1 */
+ {0x00000190, 0x07040000}, /* DFITMG0 */
+ {0x00000198, 0x07000101}, /* DFILPCFG0 */
+ {0x000001a0, 0xc0400003}, /* DFIUPD0 */
+ {0x00000240, 0x0905092c}, /* ODTCFG */
+ {0x00000244, 0x00000101}, /* ODTMAP */
+ {0x00000250, 0x00001f00}, /* SCHED */
+ {0x00000490, 0x00000001}, /* PCTRL_0 */
+ {0xffffffff, 0xffffffff}
+ }
+ },
+ {
+ {
+ {0x00000004, 0x0000008d}, /* PHYREG01 */
+ {0x00000014, 0x0000000e}, /* PHYREG05 */
+ {0x00000018, 0x00000000}, /* PHYREG06 */
+ {0x0000001c, 0x00000008}, /* PHYREG07 */
+ {0xffffffff, 0xffffffff}
+ }
+ }
+},
--- /dev/null
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xB,
+ .bk = 0x3,
+ .bw = 0x1,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x11,
+ .cs1_row = 0x11,
+ .cs0_high16bit_row = 0x0,
+ .cs1_high16bit_row = 0x0,
+ .ddrconfig = 0
+ },
+ {
+ {0x3110080d},
+ {0x08020804},
+ {0x00000602},
+ {0x00001111},
+ {0x00000054},
+ {0x00000000},
+ 0x000000ff
+ }
+ },
+ {
+ .ddr_freq = 396, /* clock rate(MHz) */
+ .dramtype = LPDDR4,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 0
+ },
+ {
+ {
+ {0x00000000, 0x81081020}, /* MSTR */
+ {0x00000064, 0x00180038}, /* RFSHTMG */
+ {0x000000d0, 0x00020184}, /* INIT0 */
+ {0x000000d4, 0x00280000}, /* INIT1 */
+ {0x000000d8, 0x00000202}, /* INIT2 */
+ {0x000000dc, 0x00240012}, /* INIT3 */
+ {0x000000e0, 0x00310000}, /* INIT4 */
+ {0x000000e8, 0x00100000}, /* INIT6 */
+ {0x000000ec, 0x00000000}, /* INIT7 */
+ {0x000000f4, 0x000f033f}, /* RANKCTL */
+ {0x00000100, 0x0d080609}, /* DRAMTMG0 */
+ {0x00000104, 0x0003040d}, /* DRAMTMG1 */
+ {0x00000108, 0x04070c0d}, /* DRAMTMG2 */
+ {0x0000010c, 0x00505000}, /* DRAMTMG3 */
+ {0x00000110, 0x04040205}, /* DRAMTMG4 */
+ {0x00000114, 0x02030303}, /* DRAMTMG5 */
+ {0x00000118, 0x01010004}, /* DRAMTMG6 */
+ {0x0000011c, 0x00000301}, /* DRAMTMG7 */
+ {0x00000120, 0x00000303}, /* DRAMTMG8 */
+ {0x00000130, 0x00020000}, /* DRAMTMG12 */
+ {0x00000134, 0x00100002}, /* DRAMTMG13 */
+ {0x00000138, 0x00000039}, /* DRAMTMG14 */
+ {0x00000180, 0x00c60006}, /* ZQCTL0 */
+ {0x00000184, 0x00a00000}, /* ZQCTL1 */
+ {0x00000190, 0x07040000}, /* DFITMG0 */
+ {0x00000198, 0x07000101}, /* DFILPCFG0 */
+ {0x000001a0, 0xc0400003}, /* DFIUPD0 */
+ {0x00000240, 0x0905092c}, /* ODTCFG */
+ {0x00000244, 0x00000101}, /* ODTMAP */
+ {0x00000250, 0x00001f00}, /* SCHED */
+ {0x00000490, 0x00000001}, /* PCTRL_0 */
+ {0xffffffff, 0xffffffff}
+ }
+ },
+ {
+ {
+ {0x00000004, 0x0000008d}, /* PHYREG01 */
+ {0x00000014, 0x0000000e}, /* PHYREG05 */
+ {0x00000018, 0x00000000}, /* PHYREG06 */
+ {0x0000001c, 0x00000008}, /* PHYREG07 */
+ {0xffffffff, 0xffffffff}
+ }
+ }
+},
--- /dev/null
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xB,
+ .bk = 0x3,
+ .bw = 0x1,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x11,
+ .cs1_row = 0x11,
+ .cs0_high16bit_row = 0x0,
+ .cs1_high16bit_row = 0x0,
+ .ddrconfig = 0
+ },
+ {
+ {0x34140b11},
+ {0x0b030804},
+ {0x00000602},
+ {0x00001111},
+ {0x00000054},
+ {0x00000000},
+ 0x000000ff
+ }
+ },
+ {
+ .ddr_freq = 528, /* clock rate(MHz) */
+ .dramtype = LPDDR4,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 0
+ },
+ {
+ {
+ {0x00000000, 0x81081020}, /* MSTR */
+ {0x00000064, 0x0020004a}, /* RFSHTMG */
+ {0x000000d0, 0x00020205}, /* INIT0 */
+ {0x000000d4, 0x00350000}, /* INIT1 */
+ {0x000000d8, 0x00000203}, /* INIT2 */
+ {0x000000dc, 0x00240012}, /* INIT3 */
+ {0x000000e0, 0x00310000}, /* INIT4 */
+ {0x000000e8, 0x00100000}, /* INIT6 */
+ {0x000000ec, 0x00000000}, /* INIT7 */
+ {0x000000f4, 0x000f033f}, /* RANKCTL */
+ {0x00000100, 0x0e0b090c}, /* DRAMTMG0 */
+ {0x00000104, 0x00030412}, /* DRAMTMG1 */
+ {0x00000108, 0x04070c0d}, /* DRAMTMG2 */
+ {0x0000010c, 0x00505000}, /* DRAMTMG3 */
+ {0x00000110, 0x05040306}, /* DRAMTMG4 */
+ {0x00000114, 0x02030404}, /* DRAMTMG5 */
+ {0x00000118, 0x01010004}, /* DRAMTMG6 */
+ {0x0000011c, 0x00000301}, /* DRAMTMG7 */
+ {0x00000120, 0x00000404}, /* DRAMTMG8 */
+ {0x00000130, 0x00020000}, /* DRAMTMG12 */
+ {0x00000134, 0x00100002}, /* DRAMTMG13 */
+ {0x00000138, 0x0000004c}, /* DRAMTMG14 */
+ {0x00000180, 0x01080008}, /* ZQCTL0 */
+ {0x00000184, 0x00e00000}, /* ZQCTL1 */
+ {0x00000190, 0x07040000}, /* DFITMG0 */
+ {0x00000198, 0x07000101}, /* DFILPCFG0 */
+ {0x000001a0, 0xc0400003}, /* DFIUPD0 */
+ {0x00000240, 0x0905092c}, /* ODTCFG */
+ {0x00000244, 0x00000101}, /* ODTMAP */
+ {0x00000250, 0x00001f00}, /* SCHED */
+ {0x00000490, 0x00000001}, /* PCTRL_0 */
+ {0xffffffff, 0xffffffff}
+ }
+ },
+ {
+ {
+ {0x00000004, 0x0000008d}, /* PHYREG01 */
+ {0x00000014, 0x0000000e}, /* PHYREG05 */
+ {0x00000018, 0x00000000}, /* PHYREG06 */
+ {0x0000001c, 0x00000008}, /* PHYREG07 */
+ {0xffffffff, 0xffffffff}
+ }
+ }
+},
--- /dev/null
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xB,
+ .bk = 0x3,
+ .bw = 0x1,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x11,
+ .cs1_row = 0x11,
+ .cs0_high16bit_row = 0x0,
+ .cs1_high16bit_row = 0x0,
+ .ddrconfig = 0
+ },
+ {
+ {0x36170d15},
+ {0x0d030805},
+ {0x00000602},
+ {0x00001111},
+ {0x00000054},
+ {0x00000000},
+ 0x000000ff
+ }
+ },
+ {
+ .ddr_freq = 664, /* clock rate(MHz) */
+ .dramtype = LPDDR4,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 1
+ },
+ {
+ {
+ {0x00000000, 0x81081020}, /* MSTR */
+ {0x00000064, 0x0028005d}, /* RFSHTMG */
+ {0x000000d0, 0x0002028a}, /* INIT0 */
+ {0x000000d4, 0x00420000}, /* INIT1 */
+ {0x000000d8, 0x00000204}, /* INIT2 */
+ {0x000000dc, 0x00240012}, /* INIT3 */
+ {0x000000e0, 0x00310000}, /* INIT4 */
+ {0x000000e8, 0x00110000}, /* INIT6 */
+ {0x000000ec, 0x00000000}, /* INIT7 */
+ {0x000000f4, 0x000f033f}, /* RANKCTL */
+ {0x00000100, 0x0f0e0b0e}, /* DRAMTMG0 */
+ {0x00000104, 0x00030415}, /* DRAMTMG1 */
+ {0x00000108, 0x04070d0d}, /* DRAMTMG2 */
+ {0x0000010c, 0x00505000}, /* DRAMTMG3 */
+ {0x00000110, 0x06040407}, /* DRAMTMG4 */
+ {0x00000114, 0x02030505}, /* DRAMTMG5 */
+ {0x00000118, 0x01010004}, /* DRAMTMG6 */
+ {0x0000011c, 0x00000301}, /* DRAMTMG7 */
+ {0x00000120, 0x00000404}, /* DRAMTMG8 */
+ {0x00000130, 0x00020000}, /* DRAMTMG12 */
+ {0x00000134, 0x00100002}, /* DRAMTMG13 */
+ {0x00000138, 0x00000060}, /* DRAMTMG14 */
+ {0x00000180, 0x014c000a}, /* ZQCTL0 */
+ {0x00000184, 0x01100000}, /* ZQCTL1 */
+ {0x00000190, 0x07040000}, /* DFITMG0 */
+ {0x00000198, 0x07000101}, /* DFILPCFG0 */
+ {0x000001a0, 0xc0400003}, /* DFIUPD0 */
+ {0x00000240, 0x0a040b28}, /* ODTCFG */
+ {0x00000244, 0x00000101}, /* ODTMAP */
+ {0x00000250, 0x00001f00}, /* SCHED */
+ {0x00000490, 0x00000001}, /* PCTRL_0 */
+ {0xffffffff, 0xffffffff}
+ }
+ },
+ {
+ {
+ {0x00000004, 0x0000008d}, /* PHYREG01 */
+ {0x00000014, 0x0000000e}, /* PHYREG05 */
+ {0x00000018, 0x00000000}, /* PHYREG06 */
+ {0x0000001c, 0x00000008}, /* PHYREG07 */
+ {0xffffffff, 0xffffffff}
+ }
+ }
+},
--- /dev/null
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xB,
+ .bk = 0x3,
+ .bw = 0x1,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x11,
+ .cs1_row = 0x11,
+ .cs0_high16bit_row = 0x0,
+ .cs1_high16bit_row = 0x0,
+ .ddrconfig = 0
+ },
+ {
+ {0x391b1019},
+ {0x10040805},
+ {0x00000602},
+ {0x00001111},
+ {0x00000054},
+ {0x00000000},
+ 0x000000ff
+ }
+ },
+ {
+ .ddr_freq = 784, /* clock rate(MHz) */
+ .dramtype = LPDDR4,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 1
+ },
+ {
+ {
+ {0x00000000, 0x81081020}, /* MSTR */
+ {0x00000064, 0x002f006e}, /* RFSHTMG */
+ {0x000000d0, 0x000202ff}, /* INIT0 */
+ {0x000000d4, 0x004e0000}, /* INIT1 */
+ {0x000000d8, 0x00000204}, /* INIT2 */
+ {0x000000dc, 0x00240012}, /* INIT3 */
+ {0x000000e0, 0x00310000}, /* INIT4 */
+ {0x000000e8, 0x00110000}, /* INIT6 */
+ {0x000000ec, 0x00000000}, /* INIT7 */
+ {0x000000f4, 0x000f033f}, /* RANKCTL */
+ {0x00000100, 0x10100d11}, /* DRAMTMG0 */
+ {0x00000104, 0x00030419}, /* DRAMTMG1 */
+ {0x00000108, 0x04070c0d}, /* DRAMTMG2 */
+ {0x0000010c, 0x00606000}, /* DRAMTMG3 */
+ {0x00000110, 0x08040409}, /* DRAMTMG4 */
+ {0x00000114, 0x02030606}, /* DRAMTMG5 */
+ {0x00000118, 0x01010004}, /* DRAMTMG6 */
+ {0x0000011c, 0x00000301}, /* DRAMTMG7 */
+ {0x00000120, 0x00000505}, /* DRAMTMG8 */
+ {0x00000130, 0x00020000}, /* DRAMTMG12 */
+ {0x00000134, 0x00100002}, /* DRAMTMG13 */
+ {0x00000138, 0x00000071}, /* DRAMTMG14 */
+ {0x00000180, 0x0188000c}, /* ZQCTL0 */
+ {0x00000184, 0x01400000}, /* ZQCTL1 */
+ {0x00000190, 0x07040000}, /* DFITMG0 */
+ {0x00000198, 0x07000101}, /* DFILPCFG0 */
+ {0x000001a0, 0xc0400003}, /* DFIUPD0 */
+ {0x00000240, 0x0a040b28}, /* ODTCFG */
+ {0x00000244, 0x00000101}, /* ODTMAP */
+ {0x00000250, 0x00001f00}, /* SCHED */
+ {0x00000490, 0x00000001}, /* PCTRL_0 */
+ {0xffffffff, 0xffffffff}
+ }
+ },
+ {
+ {
+ {0x00000004, 0x0000008d}, /* PHYREG01 */
+ {0x00000014, 0x0000000e}, /* PHYREG05 */
+ {0x00000018, 0x00000000}, /* PHYREG06 */
+ {0x0000001c, 0x00000008}, /* PHYREG07 */
+ {0xffffffff, 0xffffffff}
+ }
+ }
+},
--- /dev/null
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xB,
+ .bk = 0x3,
+ .bw = 0x1,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x11,
+ .cs1_row = 0x11,
+ .cs0_high16bit_row = 0x0,
+ .cs1_high16bit_row = 0x0,
+ .ddrconfig = 0
+ },
+ {
+ {0x3e20121d},
+ {0x12050a07},
+ {0x00000602},
+ {0x00001111},
+ {0x00000054},
+ {0x00000000},
+ 0x000000ff
+ }
+ },
+ {
+ .ddr_freq = 924, /* clock rate(MHz) */
+ .dramtype = LPDDR4,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 1
+ },
+ {
+ {
+ {0x00000000, 0x81081020}, /* MSTR */
+ {0x00000064, 0x00380082}, /* RFSHTMG */
+ {0x000000d0, 0x00020388}, /* INIT0 */
+ {0x000000d4, 0x005c0000}, /* INIT1 */
+ {0x000000d8, 0x00000205}, /* INIT2 */
+ {0x000000dc, 0x0034001b}, /* INIT3 */
+ {0x000000e0, 0x00310000}, /* INIT4 */
+ {0x000000e8, 0x00110000}, /* INIT6 */
+ {0x000000ec, 0x00000000}, /* INIT7 */
+ {0x000000f4, 0x000f033f}, /* RANKCTL */
+ {0x00000100, 0x12130f14}, /* DRAMTMG0 */
+ {0x00000104, 0x0004041e}, /* DRAMTMG1 */
+ {0x00000108, 0x050a0e0f}, /* DRAMTMG2 */
+ {0x0000010c, 0x00707000}, /* DRAMTMG3 */
+ {0x00000110, 0x0904050a}, /* DRAMTMG4 */
+ {0x00000114, 0x02040707}, /* DRAMTMG5 */
+ {0x00000118, 0x01010005}, /* DRAMTMG6 */
+ {0x0000011c, 0x00000401}, /* DRAMTMG7 */
+ {0x00000120, 0x00000606}, /* DRAMTMG8 */
+ {0x00000130, 0x00020000}, /* DRAMTMG12 */
+ {0x00000134, 0x0a100002}, /* DRAMTMG13 */
+ {0x00000138, 0x00000085}, /* DRAMTMG14 */
+ {0x00000180, 0x01ce000e}, /* ZQCTL0 */
+ {0x00000184, 0x01800000}, /* ZQCTL1 */
+ {0x00000190, 0x07070001}, /* DFITMG0 */
+ {0x00000198, 0x07000101}, /* DFILPCFG0 */
+ {0x000001a0, 0xc0400003}, /* DFIUPD0 */
+ {0x00000240, 0x0b050d3c}, /* ODTCFG */
+ {0x00000244, 0x00000101}, /* ODTMAP */
+ {0x00000250, 0x00001f00}, /* SCHED */
+ {0x00000490, 0x00000001}, /* PCTRL_0 */
+ {0xffffffff, 0xffffffff}
+ }
+ },
+ {
+ {
+ {0x00000004, 0x0000008d}, /* PHYREG01 */
+ {0x00000014, 0x00000014}, /* PHYREG05 */
+ {0x00000018, 0x00000000}, /* PHYREG06 */
+ {0x0000001c, 0x0000000a}, /* PHYREG07 */
+ {0xffffffff, 0xffffffff}
+ }
+ }
+},
struct dram_info dram_info;
struct rv1126_sdram_params sdram_configs[] = {
+#if defined(CONFIG_RAM_ROCKCHIP_LPDDR4)
+# include "sdram-rv1126-lpddr4-detect-328.inc"
+# include "sdram-rv1126-lpddr4-detect-396.inc"
+# include "sdram-rv1126-lpddr4-detect-528.inc"
+# include "sdram-rv1126-lpddr4-detect-664.inc"
+# include "sdram-rv1126-lpddr4-detect-784.inc"
+# include "sdram-rv1126-lpddr4-detect-924.inc"
+# include "sdram-rv1126-lpddr4-detect-1056.inc"
+#else
# include "sdram-rv1126-ddr3-detect-328.inc"
# include "sdram-rv1126-ddr3-detect-396.inc"
# include "sdram-rv1126-ddr3-detect-528.inc"
# include "sdram-rv1126-ddr3-detect-784.inc"
# include "sdram-rv1126-ddr3-detect-924.inc"
# include "sdram-rv1126-ddr3-detect-1056.inc"
+#endif
};
u32 common_info[] = {
projects / u-boot.git / commitdiff