x86: broadwell: Add an LPC driver

Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly
uses common code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index 39bf73395db3a69d2571fa4f4526fa19f441e0ca..3054a89165f8949b622efea828c48a6b62bc2eeb 100644 (file)
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -6,6 +6,7 @@
 
 obj-y += cpu.o
 obj-y += iobp.o
+obj-y += lpc.o
 obj-y += northbridge.o
 obj-y += pch.o
 obj-y += pinctrl_broadwell.o

diff --git a/arch/x86/cpu/broadwell/lpc.c b/arch/x86/cpu/broadwell/lpc.c
new file mode 100644 (file)
index 0000000..ee3ac18
--- /dev/null
+++ b/arch/x86/cpu/broadwell/lpc.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * From coreboot broadwell support
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pch.h>
+#include <asm/intel_regs.h>
+#include <asm/io.h>
+#include <asm/lpc_common.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/spi.h>
+
+static void set_spi_speed(void)
+{
+       u32 fdod;
+       u8 ssfc;
+
+       /* Observe SPI Descriptor Component Section 0 */
+       writel(0x1000, SPI_REG(SPIBAR_FDOC));
+
+       /* Extract the Write/Erase SPI Frequency from descriptor */
+       fdod = readl(SPI_REG(SPIBAR_FDOD));
+       fdod >>= 24;
+       fdod &= 7;
+
+       /* Set Software Sequence frequency to match */
+       ssfc = readb(SPI_REG(SPIBAR_SSFC + 2));
+       ssfc &= ~7;
+       ssfc |= fdod;
+       writeb(ssfc, SPI_REG(SPIBAR_SSFC + 2));
+}
+
+static int broadwell_lpc_early_init(struct udevice *dev)
+{
+       set_spi_speed();
+
+       return 0;
+}
+
+static int lpc_init_extra(struct udevice *dev)
+{
+       return 0;
+}
+
+static int broadwell_lpc_probe(struct udevice *dev)
+{
+       int ret;
+
+       if (!(gd->flags & GD_FLG_RELOC)) {
+               ret = lpc_common_early_init(dev);
+               if (ret) {
+                       debug("%s: lpc_early_init() failed\n", __func__);
+                       return ret;
+               }
+
+               return broadwell_lpc_early_init(dev);
+       }
+
+       return lpc_init_extra(dev);
+}
+
+static const struct udevice_id broadwell_lpc_ids[] = {
+       { .compatible = "intel,broadwell-lpc" },
+       { }
+};
+
+U_BOOT_DRIVER(broadwell_lpc_drv) = {
+       .name           = "lpc",
+       .id             = UCLASS_LPC,
+       .of_match       = broadwell_lpc_ids,
+       .probe          = broadwell_lpc_probe,
+};

diff --git a/arch/x86/include/asm/arch-broadwell/lpc.h b/arch/x86/include/asm/arch-broadwell/lpc.h
new file mode 100644 (file)
index 0000000..a718667
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/lpc.h
@@ -0,0 +1,32 @@
+/*
+ * From coreboot soc/intel/broadwell/include/soc/lpc.h
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_LPC_H
+#define _ASM_ARCH_LPC_H
+
+#define GEN_PMCON_1            0xa0
+#define  SMI_LOCK              (1 << 4)
+#define GEN_PMCON_2            0xa2
+#define  SYSTEM_RESET_STS      (1 << 4)
+#define  THERMTRIP_STS         (1 << 3)
+#define  SYSPWR_FLR            (1 << 1)
+#define  PWROK_FLR             (1 << 0)
+#define GEN_PMCON_3            0xa4
+#define  SUS_PWR_FLR           (1 << 14)
+#define  GEN_RST_STS           (1 << 9)
+#define  RTC_BATTERY_DEAD      (1 << 2)
+#define  PWR_FLR               (1 << 1)
+#define  SLEEP_AFTER_POWER_FAIL        (1 << 0)
+#define GEN_PMCON_LOCK         0xa6
+#define  SLP_STR_POL_LOCK      (1 << 2)
+#define  ACPI_BASE_LOCK                (1 << 1)
+#define PMIR                   0xac
+#define  PMIR_CF9LOCK          (1 << 31)
+#define  PMIR_CF9GR            (1 << 20)
+
+#endif