axi: ethernet: Added support for 64 bit addressing for axi-ethernet

This patch uses writeq() function to enable greater than 32 bit
addressing of axi-ethernet for the ZynqMP devices.

Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 70a2e95a8ec179cbbf1e597a39b89bb3d2dc33c0..80ed06ac66c9b950dd71939ea01df6422e911182 100644 (file)
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -78,9 +78,10 @@ static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
 struct axidma_reg {
        u32 control; /* DMACR */
        u32 status; /* DMASR */
-       u32 current; /* CURDESC */
-       u32 reserved;
-       u32 tail; /* TAILDESC */
+       u32 current; /* CURDESC low 32 bit */
+       u32 current_hi; /* CURDESC high 32 bit */
+       u32 tail; /* TAILDESC low 32 bit */
+       u32 tail_hi; /* TAILDESC high 32 bit */
 };
 
 /* Private driver structures */
@@ -168,6 +169,22 @@ static inline int mdio_wait(struct axi_regs *regs)
        return 0;
 }
 
+/**
+ * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
+ * @bd:                pointer to BD descriptor structure
+ * @desc:      Address offset of DMA descriptors
+ *
+ * This function writes the value into the corresponding Axi DMA register.
+ */
+static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
+{
+#if defined(CONFIG_PHYS_64BIT)
+       writeq(bd, desc);
+#else
+       writel((u32)bd, desc);
+#endif
+}
+
 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
                   u16 *val)
 {
@@ -465,7 +482,7 @@ static int axiemac_start(struct udevice *dev)
        writel(temp, &priv->dmarx->control);
 
        /* Start DMA RX channel. Now it's ready to receive data.*/
-       writel((u32)&rx_bd, &priv->dmarx->current);
+       axienet_dma_write(&rx_bd, &priv->dmarx->current);
 
        /* Setup the BD. */
        memset(&rx_bd, 0, sizeof(rx_bd));
@@ -485,7 +502,7 @@ static int axiemac_start(struct udevice *dev)
        writel(temp, &priv->dmarx->control);
 
        /* Rx BD is ready - start */
-       writel((u32)&rx_bd, &priv->dmarx->tail);
+       axienet_dma_write(&rx_bd, &priv->dmarx->tail);
 
        /* Enable TX */
        writel(XAE_TC_TX_MASK, &regs->tc);
@@ -527,7 +544,7 @@ static int axiemac_send(struct udevice *dev, void *ptr, int len)
 
        if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
                u32 temp;
-               writel((u32)&tx_bd, &priv->dmatx->current);
+               axienet_dma_write(&tx_bd, &priv->dmatx->current);
                /* Start the hardware */
                temp = readl(&priv->dmatx->control);
                temp |= XAXIDMA_CR_RUNSTOP_MASK;
@@ -535,7 +552,7 @@ static int axiemac_send(struct udevice *dev, void *ptr, int len)
        }
 
        /* Start transfer */
-       writel((u32)&tx_bd, &priv->dmatx->tail);
+       axienet_dma_write(&tx_bd, &priv->dmatx->tail);
 
        /* Wait for transmission to complete */
        debug("axiemac: Waiting for tx to be done\n");
@@ -626,7 +643,7 @@ static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
        flush_cache((u32)&rxframe, sizeof(rxframe));
 
        /* Rx BD is ready - start again */
-       writel((u32)&rx_bd, &priv->dmarx->tail);
+       axienet_dma_write(&rx_bd, &priv->dmarx->tail);
 
        debug("axiemac: RX completed, framelength = %d\n", length);