mmc: dw_mmc: support the DDR mode

Support the DDR mode at dw-mmc controller

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index eb4e2be5143ea3db71005f3c0522bb0dce037288..5bf36a0309d870f40be5d7d6806f0d3e0066ffb6 100644 (file)
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -284,8 +284,8 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
 
 static void dwmci_set_ios(struct mmc *mmc)
 {
-       struct dwmci_host *host = mmc->priv;
-       u32 ctype;
+       struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
+       u32 ctype, regs;
 
        debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
 
@@ -304,6 +304,14 @@ static void dwmci_set_ios(struct mmc *mmc)
 
        dwmci_writel(host, DWMCI_CTYPE, ctype);
 
+       regs = dwmci_readl(host, DWMCI_UHS_REG);
+       if (mmc->card_caps & MMC_MODE_DDR_52MHz)
+               regs |= DWMCI_DDR_MODE;
+       else
+               regs &= DWMCI_DDR_MODE;
+
+       dwmci_writel(host, DWMCI_UHS_REG, regs);
+
        if (host->clksel)
                host->clksel(host);
 }

diff --git a/include/dwmmc.h b/include/dwmmc.h
index 14c7db826912fe32be1314a8f38ff40f63cea3a8..b67f11b113fe8a66f9084e992a20c85d34906a36 100644 (file)
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -123,6 +123,9 @@
 #define DWMCI_BMOD_IDMAC_FB    (1 << 1)
 #define DWMCI_BMOD_IDMAC_EN    (1 << 7)
 
+/* UHS register */
+#define DWMCI_DDR_MODE (1 << 16)
+
 /* quirks */
 #define DWMCI_QUIRK_DISABLE_SMU                (1 << 0)