#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <common.h>
#include <miiphy.h>
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+#define PICO_MMC0 0
+#define PICO_MMC0_BLK 2
+#define PICO_MMC1 1
+#define PICO_MMC1_BLK 0
+
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
set_wdog_reset(wdog);
+#if CONFIG_IS_ENABLED(FSL_ESDHC_IMX)
+#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) || CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
+ board_late_mmc_env_init();
+#endif /* CONFIG_ENV_IS_IN_MMC or CONFIG_ENV_IS_NOWHERE */
+#endif
+
/*
* Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
* since we use PMIC_PWRON to reset the board.
}
return 0;
}
+
+#if CONFIG_IS_ENABLED(FSL_ESDHC_IMX)
+#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) || CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
+int board_mmc_get_env_dev(int devno)
+{
+ int dev_env = 0;
+
+ switch (get_boot_device()) {
+ case SD3_BOOT:
+ case MMC3_BOOT:
+ env_set("bootdev", "MMC3");
+ dev_env = PICO_MMC0;
+ break;
+ case SD1_BOOT:
+ env_set("bootdev", "SD1");
+ dev_env = PICO_MMC1;
+ break;
+ default:
+ printf("Wrong boot device!");
+ }
+
+ return dev_env;
+}
+
+int mmc_map_to_kernel_blk(int dev_no)
+{
+ int blk_no = 0;
+
+ switch (dev_no) {
+ case PICO_MMC0:
+ blk_no = PICO_MMC0_BLK;
+ break;
+ case PICO_MMC1:
+ blk_no = PICO_MMC1_BLK;
+ break;
+ default:
+ printf("Invalid MMC device!");
+ }
+
+ return blk_no;
+}
+#endif
+
+#if CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
+int mmc_get_env_dev(void)
+{
+ return board_mmc_get_env_dev(0);
+}
+#endif
+#endif /* CONFIG_FSL_ESDHC_IMX */
#include <asm/arch/sys_proto.h>
#include <asm/arch-mx7/mx7-ddr.h>
#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/gpio.h>
#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
-static iomux_v3_cfg_t const usdhc3_pads[] = {
+#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
+/* EMMC/SD */
+static const iomux_v3_cfg_t usdhc1_pads[] = {
+ MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 14)
+static const iomux_v3_cfg_t usdhc3_emmc_pads[] = {
MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR},
+ {USDHC1_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
{
- /* Assume uSDHC3 emmc is always present */
- return 1;
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ }
+
+ return ret;
}
int board_mmc_init(struct bd_info *bis)
{
- imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+ int ret;
+ u32 index;
+
+ /*
+ * Following map is done:
+ * (USDHC) (Physical Port)
+ * usdhc3 SOM MicroSD/MMC
+ * usdhc1 Carrier board MicroSD
+ * Always set boot USDHC as mmc0
+ */
+
+ imx_iomux_v3_setup_multiple_pads(usdhc3_emmc_pads,
+ ARRAY_SIZE(usdhc3_emmc_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+
+ imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+ ARRAY_SIZE(usdhc1_pads));
+ gpio_direction_input(USDHC1_CD_GPIO);
+
+ switch (get_boot_device()) {
+ case SD1_BOOT:
+ usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+ usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[1].max_bus_width = 4;
+ break;
+ case MMC3_BOOT:
+ usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[0].max_bus_width = 8;
+ usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR;
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ usdhc_cfg[1].max_bus_width = 4;
+ break;
+ case SD3_BOOT:
+ default:
+ usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+ usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR;
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ usdhc_cfg[1].max_bus_width = 4;
+ break;
+ }
+
+ for (index = 0; index < CFG_SYS_FSL_USDHC_NUM; ++index) {
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
}
#endif
projects / u-boot.git / commitdiff