stm32: migrate clock structs in include/stm32_rcc.h

In order to factorize code between STM32F4 and STM32F7
migrate all structs related to RCC clocks in include/stm32_rcc.h

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>

diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h
index 6cc19664dd3677c897350ad8e03f17e5c17a355d..e9f3aabb6fcb00c62cfd4782e87becc6b112412e 100644 (file)
--- a/arch/arm/include/asm/arch-stm32f4/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -42,41 +42,6 @@ struct stm32_u_id_regs {
        u32 u_id_high;
 };
 
-struct stm32_rcc_regs {
-       u32 cr;         /* RCC clock control */
-       u32 pllcfgr;    /* RCC PLL configuration */
-       u32 cfgr;       /* RCC clock configuration */
-       u32 cir;        /* RCC clock interrupt */
-       u32 ahb1rstr;   /* RCC AHB1 peripheral reset */
-       u32 ahb2rstr;   /* RCC AHB2 peripheral reset */
-       u32 ahb3rstr;   /* RCC AHB3 peripheral reset */
-       u32 rsv0;
-       u32 apb1rstr;   /* RCC APB1 peripheral reset */
-       u32 apb2rstr;   /* RCC APB2 peripheral reset */
-       u32 rsv1[2];
-       u32 ahb1enr;    /* RCC AHB1 peripheral clock enable */
-       u32 ahb2enr;    /* RCC AHB2 peripheral clock enable */
-       u32 ahb3enr;    /* RCC AHB3 peripheral clock enable */
-       u32 rsv2;
-       u32 apb1enr;    /* RCC APB1 peripheral clock enable */
-       u32 apb2enr;    /* RCC APB2 peripheral clock enable */
-       u32 rsv3[2];
-       u32 ahb1lpenr;  /* RCC AHB1 periph clk enable in low pwr mode */
-       u32 ahb2lpenr;  /* RCC AHB2 periph clk enable in low pwr mode */
-       u32 ahb3lpenr;  /* RCC AHB3 periph clk enable in low pwr mode */
-       u32 rsv4;
-       u32 apb1lpenr;  /* RCC APB1 periph clk enable in low pwr mode */
-       u32 apb2lpenr;  /* RCC APB2 periph clk enable in low pwr mode */
-       u32 rsv5[2];
-       u32 bdcr;       /* RCC Backup domain control */
-       u32 csr;        /* RCC clock control & status */
-       u32 rsv6[2];
-       u32 sscgr;      /* RCC spread spectrum clock generation */
-       u32 plli2scfgr; /* RCC PLLI2S configuration */
-       u32 pllsaicfgr;
-       u32 dckcfgr;
-};
-
 struct stm32_pwr_regs {
        u32 cr;
        u32 csr;

diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
index f5e08ef8f59d396841a73e77f39834a3ff3c050c..f54e6f195575c7146d6f91bc1488165d25cae7b3 100644 (file)
--- a/arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -59,41 +59,6 @@ static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
 
 #define STM32_BUS_MASK         GENMASK(31, 16)
 
-struct stm32_rcc_regs {
-       u32 cr;         /* RCC clock control */
-       u32 pllcfgr;    /* RCC PLL configuration */
-       u32 cfgr;       /* RCC clock configuration */
-       u32 cir;        /* RCC clock interrupt */
-       u32 ahb1rstr;   /* RCC AHB1 peripheral reset */
-       u32 ahb2rstr;   /* RCC AHB2 peripheral reset */
-       u32 ahb3rstr;   /* RCC AHB3 peripheral reset */
-       u32 rsv0;
-       u32 apb1rstr;   /* RCC APB1 peripheral reset */
-       u32 apb2rstr;   /* RCC APB2 peripheral reset */
-       u32 rsv1[2];
-       u32 ahb1enr;    /* RCC AHB1 peripheral clock enable */
-       u32 ahb2enr;    /* RCC AHB2 peripheral clock enable */
-       u32 ahb3enr;    /* RCC AHB3 peripheral clock enable */
-       u32 rsv2;
-       u32 apb1enr;    /* RCC APB1 peripheral clock enable */
-       u32 apb2enr;    /* RCC APB2 peripheral clock enable */
-       u32 rsv3[2];
-       u32 ahb1lpenr;  /* RCC AHB1 periph clk enable in low pwr mode */
-       u32 ahb2lpenr;  /* RCC AHB2 periph clk enable in low pwr mode */
-       u32 ahb3lpenr;  /* RCC AHB3 periph clk enable in low pwr mode */
-       u32 rsv4;
-       u32 apb1lpenr;  /* RCC APB1 periph clk enable in low pwr mode */
-       u32 apb2lpenr;  /* RCC APB2 periph clk enable in low pwr mode */
-       u32 rsv5[2];
-       u32 bdcr;       /* RCC Backup domain control */
-       u32 csr;        /* RCC clock control & status */
-       u32 rsv6[2];
-       u32 sscgr;      /* RCC spread spectrum clock generation */
-       u32 plli2scfgr; /* RCC PLLI2S configuration */
-       u32 pllsaicfgr; /* PLLSAI configuration */
-       u32 dckcfgr;    /* dedicated clocks configuration register */
-       u32 dckcfgr2;   /* dedicated clocks configuration register */
-};
 #define STM32_RCC              ((struct stm32_rcc_regs *)RCC_BASE)
 
 

diff --git a/arch/arm/mach-stm32/stm32f4/clock.c b/arch/arm/mach-stm32/stm32f4/clock.c
index 15fcadbbe6fa162b728c19e7e7ae32415ff9fdcf..774591d6a596f3db07bcea93fa4e5d3ded5a51f1 100644 (file)
--- a/arch/arm/mach-stm32/stm32f4/clock.c
+++ b/arch/arm/mach-stm32/stm32f4/clock.c
@@ -9,6 +9,7 @@
  */
 
 #include <common.h>
+#include <stm32_rcc.h>
 #include <asm/io.h>
 #include <asm/arch/stm32.h>
 #include <asm/arch/stm32_periph.h>
@@ -81,32 +82,6 @@
 #define RCC_ENR_GPIO_J_EN      (1 << 9)
 #define RCC_ENR_GPIO_K_EN      (1 << 10)
 
-struct pll_psc {
-       u8      pll_m;
-       u16     pll_n;
-       u8      pll_p;
-       u8      pll_q;
-       u8      ahb_psc;
-       u8      apb1_psc;
-       u8      apb2_psc;
-};
-
-#define AHB_PSC_1              0
-#define AHB_PSC_2              0x8
-#define AHB_PSC_4              0x9
-#define AHB_PSC_8              0xA
-#define AHB_PSC_16             0xB
-#define AHB_PSC_64             0xC
-#define AHB_PSC_128            0xD
-#define AHB_PSC_256            0xE
-#define AHB_PSC_512            0xF
-
-#define APB_PSC_1              0
-#define APB_PSC_2              0x4
-#define APB_PSC_4              0x5
-#define APB_PSC_8              0x6
-#define APB_PSC_16             0x7
-
 #if !defined(CONFIG_STM32_HSE_HZ)
 #error "CONFIG_STM32_HSE_HZ not defined!"
 #else

diff --git a/arch/arm/mach-stm32/stm32f4/timer.c b/arch/arm/mach-stm32/stm32f4/timer.c
index 1dee190766bc8b8422982f045c45077d82b1963d..163f4616d3f9f92c96a667e73c1207273eaa09f6 100644 (file)
--- a/arch/arm/mach-stm32/stm32f4/timer.c
+++ b/arch/arm/mach-stm32/stm32f4/timer.c
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <stm32_rcc.h>
 #include <asm/io.h>
 #include <asm/armv7m.h>
 #include <asm/arch/stm32.h>

diff --git a/arch/arm/mach-stm32/stm32f7/timer.c b/arch/arm/mach-stm32/stm32f7/timer.c
index 0521c24810b89d2e3e0487a291113ac9d0e68d09..69d37a7c708ce098778343c335515497506816a7 100644 (file)
--- a/arch/arm/mach-stm32/stm32f7/timer.c
+++ b/arch/arm/mach-stm32/stm32f7/timer.c
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <stm32_rcc.h>
 #include <asm/io.h>
 #include <asm/arch/stm32.h>
 #include <asm/arch/stm32_defs.h>

diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c
index d6763c306f830350ce599cbd4f28036c4e609601..6f19a0563d0e09e7c69a25c9bd45ab8ddae5fef4 100644 (file)
--- a/board/st/stm32f429-discovery/stm32f429-discovery.c
+++ b/board/st/stm32f429-discovery/stm32f429-discovery.c
@@ -13,6 +13,7 @@
 
 #include <common.h>
 #include <dm.h>
+#include <stm32_rcc.h>
 #include <asm/io.h>
 #include <asm/armv7m.h>
 #include <asm/arch/stm32.h>

diff --git a/include/stm32_rcc.h b/include/stm32_rcc.h
index fb0855268e59ec46a49b6a40b67a697fc66b1596..063177bc9877cdf4d87affba15df09dc26c79eb6 100644 (file)
--- a/include/stm32_rcc.h
+++ b/include/stm32_rcc.h
@@ -50,4 +50,42 @@ struct stm32_rcc_clk {
        enum soc_family soc;
 };
 
+struct stm32_rcc_regs {
+       u32 cr;         /* RCC clock control */
+       u32 pllcfgr;    /* RCC PLL configuration */
+       u32 cfgr;       /* RCC clock configuration */
+       u32 cir;        /* RCC clock interrupt */
+       u32 ahb1rstr;   /* RCC AHB1 peripheral reset */
+       u32 ahb2rstr;   /* RCC AHB2 peripheral reset */
+       u32 ahb3rstr;   /* RCC AHB3 peripheral reset */
+       u32 rsv0;
+       u32 apb1rstr;   /* RCC APB1 peripheral reset */
+       u32 apb2rstr;   /* RCC APB2 peripheral reset */
+       u32 rsv1[2];
+       u32 ahb1enr;    /* RCC AHB1 peripheral clock enable */
+       u32 ahb2enr;    /* RCC AHB2 peripheral clock enable */
+       u32 ahb3enr;    /* RCC AHB3 peripheral clock enable */
+       u32 rsv2;
+       u32 apb1enr;    /* RCC APB1 peripheral clock enable */
+       u32 apb2enr;    /* RCC APB2 peripheral clock enable */
+       u32 rsv3[2];
+       u32 ahb1lpenr;  /* RCC AHB1 periph clk enable in low pwr mode */
+       u32 ahb2lpenr;  /* RCC AHB2 periph clk enable in low pwr mode */
+       u32 ahb3lpenr;  /* RCC AHB3 periph clk enable in low pwr mode */
+       u32 rsv4;
+       u32 apb1lpenr;  /* RCC APB1 periph clk enable in low pwr mode */
+       u32 apb2lpenr;  /* RCC APB2 periph clk enable in low pwr mode */
+       u32 rsv5[2];
+       u32 bdcr;       /* RCC Backup domain control */
+       u32 csr;        /* RCC clock control & status */
+       u32 rsv6[2];
+       u32 sscgr;      /* RCC spread spectrum clock generation */
+       u32 plli2scfgr; /* RCC PLLI2S configuration */
+       /* below registers are only available on STM32F46x and STM32F7 SoCs*/
+       u32 pllsaicfgr; /* PLLSAI configuration */
+       u32 dckcfgr;    /* dedicated clocks configuration register */
+       /* Below registers are only available on STM32F7 SoCs */
+       u32 dckcfgr2;   /* dedicated clocks configuration register */
+};
+
 #endif /* __STM32_RCC_H_ */