clk: renesas: Add R8A77970 SD0H/SD0 clocks for SDHI

clk: renesas: Add R8A77970 SD0H/SD0 clocks for SDHI

On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on
the other R-Car gen3 SoCs. Hence, new clock types are introduced
respectively.

Based on Linux commit 381081ffc294 ("clk: renesas: r8a77970: Add SD0H/SD0
clocks for SDHI") by Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead
       - Do not modify r8a77970-cpg-mssr.c much, drop enum r8a77970_clk_types
         which is now part of common clock types in rcar-gen3-cpg.h instead