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(parent: c44f812) | patch
armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC
authorCalvin Johnson <calvin.johnson@nxp.com>
Thu, 8 Mar 2018 10:00:33 +0000 (15:30 +0530)
committerJoe Hershberger <joe.hershberger@ni.com>
Thu, 22 Mar 2018 20:05:30 +0000 (15:05 -0500)
commitc4dc68b02ff9f6c1ccb088a06cf0445e4031f093
tree8563a0797b103a7edd5007186bc7bb9cb6e46116tree | snapshot
parentc44f8125bc255f3c473d721441f1781a0d0bb1bccommit | diff
armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC

1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces
to bufferable.
2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces.
3. Disable ECC detection for PFE.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
arch/arm/cpu/armv8/fsl-layerscape/soc.c diff | blob | history
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h diff | blob | history
arch/arm/include/asm/arch-fsl-layerscape/soc.h diff | blob | history
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