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(parent: 68620c9) | patch
clk: sunxi: h3: Implement EPHY CLK and RESET
authorJagan Teki <jagan@amarulasolutions.com>
Wed, 27 Feb 2019 18:56:59 +0000 (00:26 +0530)
committerJagan Teki <jagan@amarulasolutions.com>
Sat, 9 Mar 2019 07:46:35 +0000 (13:16 +0530)
commitaefc0b7a60b9147b79b7a735c045e28daba712f1
tree0790e0977f61242f1c686b58bc20e2a9dad0eaa4tree | snapshot
parent68620c9698f109c1f001f80d282138a5c67cabefcommit | diff
clk: sunxi: h3: Implement EPHY CLK and RESET

EPHY CLK and RESET is available in Allwinner H3 EMAC
via mdio-mux node of internal PHY. Add the respective
clock and reset reg and bits.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
drivers/clk/sunxi/clk_h3.c diff | blob | history
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