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riscv: jh7110: enable riscv,timer in the device tree
authorTorsten Duwe <duwe@lst.de>
Mon, 14 Aug 2023 16:05:33 +0000 (18:05 +0200)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Tue, 5 Sep 2023 02:53:36 +0000 (10:53 +0800)
commit6164d86984cb6246680e5d94d9ec0633f2b70e98
tree6f46d4b8d5e9cad5f969665f707d0b7374ef9130tree | snapshot
parentf39f8f77a5268530e982aa38e921c640d532a9aecommit | diff
riscv: jh7110: enable riscv,timer in the device tree

The JH7110 has the arhitectural CPU timer on all 5 rv64 cores.
Note that in the device tree.

Signed-off-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/dts/jh7110.dtsi diff | blob | history
My U-Boot fork