]> git.dujemihanovic.xyz Git - u-boot.git/commit
net: gem: Remove undocumented is-internal-pcspma dt flag
authorMichal Simek <michal.simek@amd.com>
Fri, 13 Sep 2024 07:37:38 +0000 (09:37 +0200)
committerMichal Simek <michal.simek@amd.com>
Fri, 20 Sep 2024 13:31:19 +0000 (15:31 +0200)
commit6161eaf05794ab2fc1af2b0159083ab6b955e20c
treef9c9dc7f5eaaf68ca36a9e76038745cc3e280b44
parent067e0294806eb132e01f64d89a4df9a9cc857692
net: gem: Remove undocumented is-internal-pcspma dt flag

Generic understanding/consideration is that phy-mode as sgmi means that the
internal PCS(Physical Coding Sublayer) should be enabled by default.
Xilinx GEM implementation allows configuration GEM (gmii mode) + PL PCS PMA
(sgmii mode, Physical Medum Attachment) but in this case phy-mode should be
setup as gmii.
The reason for this assumption is that phy-mode should be described based
on GEM configuration not based on mode coming out of PHY.

Also Linux kernel automatically setting up PCSSEL bit when phy mode is
sgmii without a need to specified additional DT propety.
All our DTSes with sgmii phy mode have this flag enabled that's why there
is no need/reason to just duplicate information.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2ecdbcc4ce692e2f8b3e7054a2abab35f6c03a69.1726213052.git.michal.simek@amd.com
arch/arm/dts/zynqmp-dlc21-revA.dts
arch/arm/dts/zynqmp-e-a2197-00-revA.dts
arch/arm/dts/zynqmp-g-a2197-00-revA.dts
arch/arm/dts/zynqmp-p-a2197-00-revA.dts
arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
arch/arm/dts/zynqmp-vpk120-revA.dts
drivers/net/zynq_gem.c