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(parent: dd2f413) | patch
imx8mp: DDR performance tunning
authorJian Li <jian.li@nxp.com>
Mon, 20 Jan 2020 07:14:42 +0000 (15:14 +0800)
committerPeng Fan <peng.fan@nxp.com>
Tue, 14 Jul 2020 07:23:46 +0000 (15:23 +0800)
commit5865d14dde8f60f678e144e432a5e5ad223915d0
treeb4aae596e1c3df20d7bcf0eed1f1437a6d079e46tree | snapshot
parentdd2f41370d8320f40944e80b2c87734a5ee1dc44commit | diff
imx8mp: DDR performance tunning

1. set SCHED.rdwr_idle_gap=0
2. set SCHED.pageclose=1

Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Jian Li <jian.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
board/freescale/imx8mp_evk/lpddr4_timing.c diff | blob | history
My U-Boot fork