bootstage: Mark the start/end of TPL and SPL separately

bootstage: Mark the start/end of TPL and SPL separately

At present bootstage in TPL and SPL use the same ID so it is not possible
to see the timing of each. Separate out the IDs and use the correct one
depending on which phase we are at.

Example output:

Timer summary in microseconds (14 records):
       Mark    Elapsed  Stage
          0          0  reset
    224,787    224,787  TPL
    282,248     57,461  end TPL
    341,067     58,819  SPL
    925,436    584,369  end SPL
    931,710      6,274  board_init_f
  1,035,482    103,772  board_init_r
  1,387,852    352,370  main_loop
  1,387,911         59  id=175

Accumulated time:
                   196  dm_r
                 8,300  dm_spl
                14,139  dm_f
               229,121  fsp-m
               262,992  fsp-s

Signed-off-by: Simon Glass <sjg@chromium.org>