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(parent: 38b0852) | patch
mtd: spi-nor-core: Fix address width on flash chips > 16MB
authorPratyush Yadav <p.yadav@ti.com>
Fri, 25 Jun 2021 19:17:10 +0000 (00:47 +0530)
committerJagan Teki <jagan@amarulasolutions.com>
Mon, 28 Jun 2021 06:27:46 +0000 (11:57 +0530)
commit1af0334ab4effb0bd17c3b0cf1fc1b65ff4f3ef8
tree20db2ee21f1220b18fbe7b76189cacacfd5ac663tree | snapshot
parent38b0852b0eab1c5ce18ed8125572ffb0bb6973fdcommit | diff
mtd: spi-nor-core: Fix address width on flash chips > 16MB

If a flash chip has more than 16MB capacity but its BFPT reports
BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.

The check in spi_nor_scan() doesn't catch it because addr_width did get
set. This fixes that check.

Ported from Kernel commit 324f78dfb442b82365548b657ec4e6974c677502.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
drivers/mtd/spi/spi-nor-core.c diff | blob | history
My U-Boot fork