]> git.dujemihanovic.xyz Git - u-boot.git/commit
clk: renesas: Add RZ/G2L & RZ/G2LC CPG driver
authorPaul Barker <paul.barker.ct@bp.renesas.com>
Mon, 16 Oct 2023 09:25:29 +0000 (10:25 +0100)
committerMarek Vasut <marek.vasut+renesas@mailbox.org>
Mon, 16 Oct 2023 13:46:18 +0000 (15:46 +0200)
commit1918ff5c95bef489e8d025f73b902af6794e4d28
treeb0d91ab081ad5684666202c07d38dca30b7fefd6
parenta4b3e0865218078f5061383884d927f8f4d0fc72
clk: renesas: Add RZ/G2L & RZ/G2LC CPG driver

This driver provides clock and reset control for the Renesas R9A07G044L
(RZ/G2L) and R9A07G044C (RZ/G2LC) SoC. It consists of two parts:

* driver code which is applicable to all SoCs in the RZ/G2L family.

* static data describing the clocks and resets which are specific to the
  R9A07G044{L,C} SoCs. The identifier r9a07g044 (without a final letter)
  is used to indicate that both SoCs are supported.

clk_set_rate() and clk_get_rate() are implemented only for the clocks
that are actually used in u-boot.

The CPG driver is marked with DM_FLAG_PRE_RELOC to ensure that its bind
function is called before the SCIF (serial port) driver is probed. This
is required so that we can de-assert the relevant reset signal during
the serial driver probe function.

This patch is based on the corresponding Linux v6.5 driver
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
arch/arm/mach-rmobile/Kconfig
arch/arm/mach-rmobile/Kconfig.rzg2l
drivers/clk/renesas/Kconfig
drivers/clk/renesas/Makefile
drivers/clk/renesas/r9a07g044-cpg.c [new file with mode: 0644]
drivers/clk/renesas/rzg2l-cpg.c [new file with mode: 0644]
drivers/clk/renesas/rzg2l-cpg.h [new file with mode: 0644]