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(parent: 2085ae7) | patch
ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE
authorAlexander Stein <alexanders83@web.de>
Fri, 24 Jul 2015 07:22:11 +0000 (09:22 +0200)
committerTom Rini <trini@konsulko.com>
Thu, 13 Aug 2015 00:47:41 +0000 (20:47 -0400)
commit060f9bf57b1dc1f9260bc1b999d054141b87d7d2
treeac71ebcf77ce3b3c9e163542dc06d16e28fa6a64tree | snapshot
parent2085ae74dee47ed3da63416aac0305936b43eeeacommit | diff
ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE

The cacheline is always 32 bytes for arm1176 CPUs, so define it at board
config level for cache handling code.
The ARM Cortex-A7 has a dcache line size of 64 bytes.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
include/configs/rpi.h diff | blob | history
include/configs/rpi_2.h diff | blob | history
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