From 8b40f22900f3618ab1b83d15d078ab6f75c7c800 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Date: Wed, 25 Apr 2018 14:25:42 +0800 Subject: [PATCH] armv8/fsl-lsch2: make the workaround for PIN MUX erratum A010539 robust Mask HRESET_B after cleared the the RCW_SRC, because in the workaround we override the RCW_SRC and if HRESET_B is issued after the override then SoC cannot find valid RCW as the RCW_SRC was overwritten and result in hang. So we need to mask HRESET_B in case user asserts it, and the PORESET_B should be asserted which leads to resampling of cfg_rcw_src pins and loading of correct RCW_SRC. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 06fdd17604..bfd663942a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -517,6 +517,7 @@ static void erratum_a010539(void) porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), porsr1); + out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff); #endif } -- 2.39.5