From 4571c519b4581cffc49f40d4066c328df4d6cdf0 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Sat, 5 Mar 2016 17:32:29 +0530
Subject: [PATCH] ARM: DRA7: emif: Fix DDR init sequence during warm reset
Commit (20fae0a - ARM: DRA7: DDR: Enable SR in Power Management Control)
enables Self refresh mode by default and during warm reset the EMIF
contents are preserved. After warm reset EMIF sees that it is idle and
puts DDR in self-refresh. When in SR, leveling operations cannot be done
as DDR can only accept SR exit command, so its hanging during warm reset.
In order to fix this reset the power management control register before
EMIF initialization if it is a warm reset.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
arch/arm/cpu/armv7/omap-common/emif-common.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 90c241a007..6b33b45e7c 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -327,8 +327,10 @@ static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- if (warm_reset())
+ if (warm_reset()) {
emif_reset_phy(base);
+ writel(0x0, &emif->emif_pwr_mgmt_ctrl);
+ }
do_ext_phy_settings(base, regs);
writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
--
2.39.5