From: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Date: Wed, 19 Jul 2023 08:49:12 +0000 (-0600)
Subject: clk: zynqmp: Add set_rate support for gem rx and tsu clks
X-Git-Tag: v2025.01-rc5-pxa1908~931^2~2
X-Git-Url: http://git.dujemihanovic.xyz/img/static/html/index.html?a=commitdiff_plain;h=7a480fd995e279dd883b9e4e24741f9c71d66143;p=u-boot.git

clk: zynqmp: Add set_rate support for gem rx and tsu clks

gem0_rx till gem3_rx  and gem_tsu are missing from set rate function.
Add them, so that they can be set from pmu firmware via clock framework.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230719084912.30209-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 8320d49184..53327cf9ad 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -719,6 +719,8 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
 	switch (id) {
 	case gem0_ref ... gem3_ref:
 	case gem0_tx ... gem3_tx:
+	case gem0_rx ... gem3_rx:
+	case gem_tsu:
 	case qspi_ref ... can1_ref:
 	case usb0_bus_ref ... usb3_dual_ref:
 		return zynqmp_clk_set_peripheral_rate(priv, id,