From: Xie Xiaobo <r63061@freescale.com>
Date: Fri, 9 Mar 2007 11:08:25 +0000 (+0800)
Subject: Fix two bugs for MPC83xx DDR2 controller SPD Init
X-Git-Tag: v2025.01-rc5-pxa1908~22755^2~2^2~12
X-Git-Url: http://git.dujemihanovic.xyz/img/static/html/index.html?a=commitdiff_plain;h=6fbf261f8df294e589cfadebebe5468e3c0f29e9;p=u-boot.git

Fix two bugs for MPC83xx DDR2 controller SPD Init

There are a few bugs in the cpu/mpc83xx/spd_sdram.c
the first bug is that the picos_to_clk routine introduces a huge
rounding error in 83xx.
the second bug is that the mode register write recovery field is
tWR-1, not tWR >> 1.
---

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index d9b8753ca0..41a1f1fc7b 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -58,8 +58,8 @@ picos_to_clk(int picos)
 	int clks;
 
 	ddr_bus_clk = gd->ddr_clk >> 1;
-	clks = picos / ((1000000000 / ddr_bus_clk) * 1000);
-	if (picos % ((1000000000 / ddr_bus_clk) * 1000) != 0)
+	clks = picos / (1000000000 / (ddr_bus_clk / 1000));
+	if (picos % (1000000000 / (ddr_bus_clk / 1000)) != 0)
 		clks++;
 
 	return clks;
@@ -624,7 +624,7 @@ long int spd_sdram()
 			 | (1 << (16 + 10))             /* DQS Differential disable */
 			 | (add_lat << (16 + 3))        /* Additive Latency in EMRS1 */
 			 | (mode_odt_enable << 16)      /* ODT Enable in EMRS1 */
-			 | ((twr_clk >> 1) << 9)        /* Write Recovery Autopre */
+			 | ((twr_clk - 1) << 9)         /* Write Recovery Autopre */
 			 | (caslat << 4)                /* caslat */
 			 | (burstlen << 0)              /* Burst length */
 			);