From d652a344a009854b72d7df97c11d2582b9e11c9a Mon Sep 17 00:00:00 2001
From: Ben Gardiner <bengardiner@nanometrics.ca>
Date: Mon, 16 Jan 2012 07:43:15 +0000
Subject: [PATCH] arm, davinci: add PLL0 prediv to da850 lowlevel setup
The OMAP-L138 has a pre-divider available on PLL0.
Add support to da850_lowlevel.c for configuring PLL0's pre-divider. This is
to achieve certain OPP's -- e.g. the 372MHz OPP used also by Linux.
Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Cc: Christian Riesch <christian.riesch@omicron.at>
CC: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
---
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 7 +++++++
arch/arm/include/asm/arch-davinci/pll_defs.h | 3 ++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
index a532f8ab60..eec06bc54d 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -85,6 +85,13 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
/* Enable the PLL from Disable Mode PLLDIS bit to 0 */
clrbits_le32(®->pllctl, PLLCTL_PLLDIS);
+#if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
+ /* program the prediv */
+ if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
+ writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV),
+ ®->prediv);
+#endif
+
/* Program the required multiplier value in PLLM */
writel(pllmult, ®->pllm);
diff --git a/arch/arm/include/asm/arch-davinci/pll_defs.h b/arch/arm/include/asm/arch-davinci/pll_defs.h
index f1396e3194..1c8d83fb5b 100644
--- a/arch/arm/include/asm/arch-davinci/pll_defs.h
+++ b/arch/arm/include/asm/arch-davinci/pll_defs.h
@@ -68,7 +68,8 @@ struct dv_pll_regs {
#define PLLCTL_RES_9 (1 << 8)
#define PLLCTL_EXTCLKSRC (1 << 9)
-#define PLL_POSTDEN (1 << 15)
+#define PLL_DIVEN (1 << 15)
+#define PLL_POSTDEN PLL_DIVEN
#define PLL_SCSCFG3_DIV45PENA (1 << 2)
#define PLL_SCSCFG3_EMA_CLKSRC (1 << 1)
--
2.39.5