From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 4 Aug 2023 09:33:59 +0000 (+0000)
Subject: clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div
X-Git-Tag: v2025.01-rc5-pxa1908~887^2~10
X-Git-Url: http://git.dujemihanovic.xyz/img/static/html/%7B%7B?a=commitdiff_plain;h=6da8400d7ae986ef2a8e0ddb4f39907c6c0666f1;p=u-boot.git

clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div

The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.

Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.

Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
index 76f1ad5510..9c7ddd751f 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
@@ -495,7 +495,7 @@ enum {
 
 	/* CRU_CLK_SEL81_CON */
 	CPLL_25M_DIV_SHIFT		= 8,
-	CPLL_25M_DIV_MASK		= 0x1f << CPLL_25M_DIV_SHIFT,
+	CPLL_25M_DIV_MASK		= 0x3f << CPLL_25M_DIV_SHIFT,
 	CPLL_50M_DIV_SHIFT		= 0,
 	CPLL_50M_DIV_MASK		= 0x1f << CPLL_50M_DIV_SHIFT,
 
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
index e8e4d20e53..dab254d4d1 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -702,7 +702,10 @@ static ulong rk3568_cpll_div_set_rate(struct rk3568_clk_priv *priv,
 	}
 
 	div = DIV_ROUND_UP(priv->cpll_hz, rate);
-	assert(div - 1 <= 31);
+	if (clk_id == CPLL_25M)
+		assert(div - 1 <= 63);
+	else
+		assert(div - 1 <= 31);
 	rk_clrsetreg(&cru->clksel_con[con],
 		     mask, (div - 1) << shift);
 	return rk3568_cpll_div_get_rate(priv, clk_id);