From: Michal Simek <michal.simek@amd.com>
Date: Wed, 23 Oct 2024 06:09:23 +0000 (+0200)
Subject: arm64: zynqmp: Configure SoC RTC on SOM
X-Git-Tag: v2025.01-rc5-pxa1908~96^2~15
X-Git-Url: http://git.dujemihanovic.xyz/img/static/html/%7B%7B?a=commitdiff_plain;h=4de127a44a45a8135756d4a7f26919393b91bb32;p=u-boot.git
arm64: zynqmp: Configure SoC RTC on SOM
Use RTC available in HW on Kria SOM without using emulation that's why
configure it properly and disable emulated one.
Power on reset value of RTC Calibration register without battery backup is
not matching with crystal frequency which leads to RTC time drift. That's
why write CALIB_WRITE register with crystal frequency (0x7FFF). There is
also an option to write zero so that Linux will set default value (0x7FFF)
in driver probe but calibration 0 is not permited by DT schema.
Co-developed-by: Srinivas Goud <srinivas.goud@amd.com>
Signed-off-by: Srinivas Goud <srinivas.goud@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9b684faeec85381b9b8fe796aaebc2ee79f17b8e.1729663761.git.michal.simek@amd.com
---
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 8056f6b176..8c43ade940 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -387,6 +387,7 @@
&rtc {
status = "okay";
+ calibration = <0x7fff>;
};
&lpd_dma_chan1 {
diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig
index dd4df0b2da..0dddf69c5d 100644
--- a/configs/xilinx_zynqmp_kria_defconfig
+++ b/configs/xilinx_zynqmp_kria_defconfig
@@ -187,7 +187,6 @@ CONFIG_DM_PWM=y
CONFIG_PWM_CADENCE_TTC=y
CONFIG_RESET_ZYNQMP=y
CONFIG_DM_RTC=y
-CONFIG_RTC_EMULATION=y
CONFIG_RTC_ZYNQMP=y
CONFIG_SCSI=y
CONFIG_ARM_DCC=y