From: Damon Ding <damon.ding@rock-chips.com>
Date: Fri, 4 Aug 2023 09:33:57 +0000 (+0000)
Subject: clk: rockchip: rk3568: Fix clk selection in rk3568_pwm_get_clk
X-Git-Tag: v2025.01-rc5-pxa1908~887^2~11
X-Git-Url: http://git.dujemihanovic.xyz/img/static/html/%7B%7B%20%24.Site.BaseURL%20%7D%7Dposts/%7B%7B%20%28.OutputFormats.Get?a=commitdiff_plain;h=acb9812034850ae0d737a767b392b9cd097f3606;p=u-boot.git

clk: rockchip: rk3568: Fix clk selection in rk3568_pwm_get_clk

Fix use of wrong clk selection for CLK_PWM1 on RK3568.

Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---

diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
index 0df82f5971..e8e4d20e53 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -1142,7 +1142,7 @@ static ulong rk3568_pwm_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
 
 	switch (clk_id) {
 	case CLK_PWM1:
-		sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;
+		sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;
 		break;
 	case CLK_PWM2:
 		sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;