From 9c4b0131d1d06dc87cecd08f065ec9b5c0f08b0f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 19 Mar 2019 07:14:37 -0400 Subject: [PATCH] ti: keystone2: Move CONFIG_ISW_ENTRY_ADDR to a common place The ISW_ENTRY_ADDR Kconfig option under mach-omap2 isn't a SoC specific notion but rather "where is our previous stage loaded in memory?" option. Make use of this on ARCH_KEYSTONE rather than SPL_TEXT_BASE for our HS builds that are not using SPL anyhow. Cc: Vitaly Andrianov Cc: Andrew F. Davis Cc: Lokesh Vutla Signed-off-by: Tom Rini Reviewed-by: Lokesh Vutla -/* SPL SPI Loader Configuration */ -#define CONFIG_SPL_TEXT_BASE 0x0c100000 - - #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS /* NAND Configuration */ diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index b1aec98a37..3ec5a5acf5 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -72,9 +72,6 @@ "bootm ${fit_loadaddr}#${name_fdt}" #endif -/* SPL SPI Loader Configuration */ -#define CONFIG_SPL_TEXT_BASE 0x0c0a0000 - /* NAND Configuration */ #define CONFIG_SYS_NAND_PAGE_2K diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 0b909a1bf6..d4f2e96bab 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -40,9 +40,6 @@ #include -/* SPL SPI Loader Configuration */ -#define CONFIG_SPL_TEXT_BASE 0x0c200000 - #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS /* NAND Configuration */ diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index 59e6b09673..cfdb36e2d7 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -40,9 +40,6 @@ #include -/* SPL SPI Loader Configuration */ -#define CONFIG_SPL_TEXT_BASE 0x0c100000 - #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS /* NAND Configuration */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 52638cef4b..eeca085f9f 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -22,7 +22,7 @@ /* Memory Configuration */ #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE - \ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_ISW_ENTRY_ADDR - \ GENERATED_GBL_DATA_SIZE) #ifdef CONFIG_SYS_MALLOC_F_LEN @@ -32,9 +32,10 @@ #endif /* SPL SPI Loader Configuration */ +#define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR #define CONFIG_SPL_PAD_TO 65536 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) -#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \ +#define CONFIG_SPL_BSS_START_ADDR (CONFIG_ISW_ENTRY_ADDR + \ CONFIG_SPL_MAX_SIZE) #define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ -- 2.39.5