From 9657841010cae49b1f903adf198ec334cfc92f11 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz> Date: Wed, 8 Apr 2020 12:02:07 +0200 Subject: [PATCH] arm: mvebu: turris_mox: don't use hardcoded addresses MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Use macro MVEBU_REGISTER to access register addresses instead of hardcoded addresses. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> --- board/CZ.NIC/turris_mox/mox_sp.c | 14 ++++++++------ board/CZ.NIC/turris_mox/turris_mox.c | 11 ++++++----- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/board/CZ.NIC/turris_mox/mox_sp.c b/board/CZ.NIC/turris_mox/mox_sp.c index 0b29ffcc67..3c23471e65 100644 --- a/board/CZ.NIC/turris_mox/mox_sp.c +++ b/board/CZ.NIC/turris_mox/mox_sp.c @@ -4,15 +4,17 @@ */ #include <common.h> +#include <asm/arch/soc.h> #include <asm/io.h> -#define RWTM_CMD_PARAM(i) (size_t)(0xd00b0000 + (i) * 4) -#define RWTM_CMD 0xd00b0040 -#define RWTM_CMD_RETSTATUS 0xd00b0080 -#define RWTM_CMD_STATUS(i) (size_t)(0xd00b0084 + (i) * 4) +#define RWTM_BASE (MVEBU_REGISTER(0xb0000)) +#define RWTM_CMD_PARAM(i) (size_t)(RWTM_BASE + (i) * 4) +#define RWTM_CMD (RWTM_BASE + 0x40) +#define RWTM_CMD_RETSTATUS (RWTM_BASE + 0x80) +#define RWTM_CMD_STATUS(i) (size_t)(RWTM_BASE + 0x84 + (i) * 4) -#define RWTM_HOST_INT_RESET 0xd00b00c8 -#define RWTM_HOST_INT_MASK 0xd00b00cc +#define RWTM_HOST_INT_RESET (RWTM_BASE + 0xc8) +#define RWTM_HOST_INT_MASK (RWTM_BASE + 0xcc) #define SP_CMD_COMPLETE BIT(0) #define MBOX_STS_SUCCESS (0x0 << 30) diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 6e937826d0..cd39b1c01f 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -5,6 +5,7 @@ #include <common.h> #include <init.h> +#include <asm/arch/soc.h> #include <asm/gpio.h> #include <asm/io.h> #include <dm.h> @@ -28,11 +29,11 @@ #define MOX_MODULE_USB3 0x5 #define MOX_MODULE_PASSPCI 0x6 -#define ARMADA_37XX_NB_GPIO_SEL 0xd0013830 -#define ARMADA_37XX_SPI_CTRL 0xd0010600 -#define ARMADA_37XX_SPI_CFG 0xd0010604 -#define ARMADA_37XX_SPI_DOUT 0xd0010608 -#define ARMADA_37XX_SPI_DIN 0xd001060c +#define ARMADA_37XX_NB_GPIO_SEL (MVEBU_REGISTER(0x13830)) +#define ARMADA_37XX_SPI_CTRL (MVEBU_REGISTER(0x10600)) +#define ARMADA_37XX_SPI_CFG (MVEBU_REGISTER(0x10604)) +#define ARMADA_37XX_SPI_DOUT (MVEBU_REGISTER(0x10608)) +#define ARMADA_37XX_SPI_DIN (MVEBU_REGISTER(0x1060c)) #define ETH1_PATH "/soc/internal-regs@d0000000/ethernet@40000" #define MDIO_PATH "/soc/internal-regs@d0000000/mdio@32004" -- 2.39.5