From 4d0c8db74d83e43dec4e7481b2d1e194f51d907b Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Tue, 4 Apr 2023 13:09:36 +0200 Subject: [PATCH] board: cssi: Add CPU board CMPCPRO CSSI has another CPU board, similar to the CMPC885 board that get plugged on the two base boards MCR3000_2G and MIAE. That CPU board is called CMPCPRO because it has a MPC8321E CPU, also known as Power QUICC II PRO. Signed-off-by: Christophe Leroy --- arch/powerpc/cpu/mpc83xx/Kconfig | 5 + arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/cmpcpro.dts | 189 +++++++++++++++ board/cssi/MAINTAINERS | 2 + board/cssi/cmpcpro/Kconfig | 26 ++ board/cssi/cmpcpro/Makefile | 8 + board/cssi/cmpcpro/cmpcpro.c | 404 +++++++++++++++++++++++++++++++ board/cssi/cmpcpro/cmpcpro.env | 8 + board/cssi/cmpcpro/nand.c | 43 ++++ configs/CMPCPRO_defconfig | 209 ++++++++++++++++ include/configs/cmpcpro.h | 99 ++++++++ 11 files changed, 994 insertions(+) create mode 100644 arch/powerpc/dts/cmpcpro.dts create mode 100644 board/cssi/cmpcpro/Kconfig create mode 100644 board/cssi/cmpcpro/Makefile create mode 100644 board/cssi/cmpcpro/cmpcpro.c create mode 100644 board/cssi/cmpcpro/cmpcpro.env create mode 100644 board/cssi/cmpcpro/nand.c create mode 100644 configs/CMPCPRO_defconfig create mode 100644 include/configs/cmpcpro.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index b695c7e4d8..582e141221 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -20,6 +20,10 @@ choice prompt "Target select" optional +config TARGET_CMPCPRO + bool "Support CMPCPRO board from CSSI" + select ARCH_MPC832X + config TARGET_MPC837XERDB bool "Support MPC837XERDB" select ARCH_MPC837X @@ -205,5 +209,6 @@ config NEVER_ASSERT_ODT_TO_CPU source "board/freescale/mpc837xerdb/Kconfig" source "board/gdsys/mpc8308/Kconfig" +source "board/cssi/cmpcpro/Kconfig" endmenu diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 26b592b85d..bb436f02bc 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -30,6 +30,7 @@ dtb-$(CONFIG_TARGET_TUXX1) += kmtuxa1.dtb dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb dtb-$(CONFIG_TARGET_CMPC885) += cmpc885.dtb +dtb-$(CONFIG_TARGET_CMPCPRO) += cmpcpro.dtb include $(srctree)/scripts/Makefile.dts diff --git a/arch/powerpc/dts/cmpcpro.dts b/arch/powerpc/dts/cmpcpro.dts new file mode 100644 index 0000000000..c27d9dba33 --- /dev/null +++ b/arch/powerpc/dts/cmpcpro.dts @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * CMPC885 Device Tree Source + * + * Copyright 2020 CS GROUP France + * + */ + +/dts-v1/; + +#include + +/ { + model = "CMPCPRO"; + compatible = "fsl, cmpc85xx", "fsl,mod85xx", "CMPCPRO", "MPC8321E", "fsl,cmpcpro"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + stdout-path = &serial0; + }; + WDT: watchdog@0 { + device_type = "watchdog"; + compatible = "fsl,pq1-wdt"; + }; + + aliases { + ethernet0 = ð0; + etehrnet1 = ð1; + serial0 = &serial0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + PowerPC,8321@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <0x20>; // 32 bytes + i-cache-line-size = <0x20>; // 32 bytes + d-cache-size = <16384>; // L1, 16K + i-cache-size = <16384>; // L1, 16K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + soc8321@b0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + ranges = <0x0 0xb0000000 0x00100000>; + reg = <0xb0000000 0x00000200>; + bus-frequency = <0>; + pmc: power@b00 { + compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc"; + reg = <0xb00 0x100 0xa00 0x100>; + interrupts = <80 0x8>; + interrupt-parent = <&ipic>; + }; + serial0: serial@4500 { + clocks = <&socclocks MPC83XX_CLK_CSB>; + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + }; + ipic:pic@700 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x700 0x100>; + device_type = "ipic"; + }; + par_io@1400 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1400 0x100>; + ranges; + compatible = "fsl,mpc8323-qe-pario","simple-bus"; + device_type = "par_io"; + num-ports = <7>; + qe_pio_a: gpio-controller@1400 { + #gpio-cells = <2>; + compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio"; + reg = <0x1400 0x18>; + gpio-controller; + }; + qe_pio_b: gpio-controller@1418 { + #gpio-cells = <2>; + compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio"; + reg = <0x1418 0x18>; + gpio-controller; + }; + qe_pio_c: gpio-controller@1430 { + #gpio-cells = <2>; + compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio"; + reg = <0x1430 0x18>; + gpio-controller; + }; + qe_pio_d: gpio-controller@1448 { + #gpio-cells = <2>; + compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio"; + reg = <0x1448 0x18>; + gpio-controller; + }; + }; + }; + socclocks: clocks { + bootph-all; + compatible = "fsl,mpc832x-clk"; + #clock-cells = <1>; + }; + qe@b0100000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe","simple-bus"; + ranges = <0x0 0xb0100000 0x00100000>; + reg = <0xb0100000 0x480>; + brg-frequency = <0>; + bus-frequency = <198000000>; + fsl,qe-num-riscs = <1>; + fsl,qe-num-snums = <28>; + spi@4c0 { + clocks = <&socclocks MPC83XX_CLK_CSB>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,mpc832x-spi"; + reg = <0x4c0 0x40>; + mode = "cpu"; + gpios = <&qe_pio_d 3 1>; + clock-frequency = <0>; + eeprom@3 { + compatible = "atmel,at25", "cs,eeprom"; + cell-index = <1>; + }; + }; + eth0: ucc@3000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <2>; + reg = <0x3000 0x200>; + rx-clock-name = "clk17"; + tx-clock-name = "clk17"; + phy-handle = <&phy1>; + phy-connection-type = "rmii"; + }; + eth1: ucc@2200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <3>; + reg = <0x2200 0x200>; + rx-clock-name = "clk12"; + tx-clock-name = "clk12"; + phy-handle = <&phy2>; + phy-connection-type = "rmii"; + }; + mdio@3120 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3120 0x18>; + compatible = "fsl,ucc-mdio"; + phy1:ethernet-phy@1 { + interrupt-parent = <&ipic>; + reg = <0x1>; + interrupts = <17 8>; + device_type = "ethernet-phy"; + }; + phy2:ethernet-phy@2 { + interrupt-parent = <&ipic>; + reg = <0x2>; + interrupts = <17 8>; + device_type = "ethernet-phy"; + }; + }; + }; +}; diff --git a/board/cssi/MAINTAINERS b/board/cssi/MAINTAINERS index d8e7b5e9b6..f82dd3b789 100644 --- a/board/cssi/MAINTAINERS +++ b/board/cssi/MAINTAINERS @@ -6,3 +6,5 @@ F: include/configs/mcr3000.h F: configs/MCR3000_defconfig F: include/configs/cmpc885.h F: configs/CMPC885_defconfig +F: include/configs/cmpcpro.h +F: configs/CMPCPRO_defconfig diff --git a/board/cssi/cmpcpro/Kconfig b/board/cssi/cmpcpro/Kconfig new file mode 100644 index 0000000000..b5d998ae5a --- /dev/null +++ b/board/cssi/cmpcpro/Kconfig @@ -0,0 +1,26 @@ +if TARGET_CMPCPRO + +config SYS_BOARD + default "cmpcpro" + +config SYS_VENDOR + default "cssi" + +config SYS_CONFIG_NAME + default "cmpcpro" + +config TEXT_BASE + default 0x40000000 + +config CPLD_BASE + hex + default 0x90000000 + +config FPGA_BASE + hex + default 0x80000000 + +config PCI + default no + +endif diff --git a/board/cssi/cmpcpro/Makefile b/board/cssi/cmpcpro/Makefile new file mode 100644 index 0000000000..73ff451ea1 --- /dev/null +++ b/board/cssi/cmpcpro/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cmpcpro.o nand.o ../common/common.o diff --git a/board/cssi/cmpcpro/cmpcpro.c b/board/cssi/cmpcpro/cmpcpro.c new file mode 100644 index 0000000000..3e9ba6a4cc --- /dev/null +++ b/board/cssi/cmpcpro/cmpcpro.c @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2006-2023 CS GROUP France + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "../common/common.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define ADDR_FPGA_BASE ((unsigned char __iomem *)CONFIG_CPLD_BASE) +#define ADDR_FPGA_RESET_G (ADDR_FPGA_BASE + 0x40) +#define ADDR_FPGA_REG_ETAT (ADDR_FPGA_BASE + 0x42) + +#define R_ETAT_PRES_BASE 0x01 +#define RESET_G_OK 0x08 + +/* SPI EEPROM parameters */ +#define MAX_SPI_BYTES 0x28 +#define EE_OFF_MAC1 0x10 +#define EE_OFF_MAC2 0x16 +#define EE_OFF_MAC3 0x1C + +static uint upma_table[] = { + /* Read Single-Beat (RSS) */ + 0x00AC0C00, 0x00FC1C40, 0x30FCE045, 0xFFFF0C00, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* Read Burst (RBS) */ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* Write Single-Beat (WSS) */ + 0x00A30C00, 0x00F31C40, 0x3FF3C045, 0xFFFF0C00, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* Write Burst (WBS) */ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* Refresh Timer (RTS) */ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* Exception Condition (EXS) */ + 0xFFFF0C01, 0xFFFF0C01, 0xFFFF0C01, 0xFFFF0C01, +}; + +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* ETH3 */ + {1, 0, 1, 0, 1}, /* TxD0 */ + {1, 1, 1, 0, 1}, /* TxD1 */ + {1, 2, 1, 0, 1}, /* TxD2 */ + {1, 3, 1, 0, 1}, /* TxD3 */ + {1, 9, 1, 0, 1}, /* TxER */ + {1, 12, 1, 0, 1}, /* TxEN */ + {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ + + {1, 4, 2, 0, 1}, /* RxD0 */ + {1, 5, 2, 0, 1}, /* RxD1 */ + {1, 6, 2, 0, 1}, /* RxD2 */ + {1, 7, 2, 0, 1}, /* RxD3 */ + {1, 8, 2, 0, 1}, /* RxER */ + {1, 10, 2, 0, 1}, /* RxDV */ + {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ + {1, 11, 2, 0, 1}, /* COL */ + {1, 13, 2, 0, 1}, /* CRS */ + + /* ETH4 */ + {1, 18, 1, 0, 1}, /* TxD0 */ + {1, 19, 1, 0, 1}, /* TxD1 */ + {1, 20, 1, 0, 1}, /* TxD2 */ + {1, 21, 1, 0, 1}, /* TxD3 */ + {1, 27, 1, 0, 1}, /* TxER */ + {1, 30, 1, 0, 1}, /* TxEN */ + {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */ + + {1, 22, 2, 0, 1}, /* RxD0 */ + {1, 23, 2, 0, 1}, /* RxD1 */ + {1, 24, 2, 0, 1}, /* RxD2 */ + {1, 25, 2, 0, 1}, /* RxD3 */ + {1, 26, 1, 0, 1}, /* RxER */ + {1, 28, 2, 0, 1}, /* Rx_DV */ + {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */ + {1, 29, 2, 0, 1}, /* COL */ + {1, 31, 2, 0, 1}, /* CRS */ + + {3, 4, 3, 0, 2}, /* MDIO */ + {3, 5, 1, 0, 2}, /* MDC */ + + {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ +}; + +void iop_setup_miae(void) +{ + immap_t __iomem *im = (immap_t *)CONFIG_SYS_IMMR; + + /* PORTA configuration */ + out_be32(&im->qepio.ioport[0].pdat, 0x00808000); + out_be32(&im->qepio.ioport[0].podr, 0x00008000); + out_be32(&im->qepio.ioport[0].dir1, 0x40800968); + out_be32(&im->qepio.ioport[0].dir2, 0x650A0896); + out_be32(&im->qepio.ioport[0].ppar1, 0x40400204); + out_be32(&im->qepio.ioport[0].ppar2, 0x05050464); + + /* PORTB configuration */ + out_be32(&im->qepio.ioport[1].pdat, 0x00018000); + out_be32(&im->qepio.ioport[1].podr, 0x00000000); + out_be32(&im->qepio.ioport[1].dir1, 0x50A08949); + out_be32(&im->qepio.ioport[1].dir2, 0x5C0C6890); + out_be32(&im->qepio.ioport[1].ppar1, 0x50504644); + out_be32(&im->qepio.ioport[1].ppar2, 0x080800A0); + + /* PORTC configuration */ + out_be32(&im->qepio.ioport[2].pdat, 0x3D000108); + out_be32(&im->qepio.ioport[2].podr, 0x00000000); + out_be32(&im->qepio.ioport[2].dir1, 0x45518000); + out_be32(&im->qepio.ioport[2].dir2, 0xA8119561); + out_be32(&im->qepio.ioport[2].ppar1, 0x80008000); + out_be32(&im->qepio.ioport[2].ppar2, 0x00000000); + + /* PORTD configuration */ + out_be32(&im->qepio.ioport[3].pdat, 0x1000E000); + out_be32(&im->qepio.ioport[3].podr, 0x0000E000); + out_be32(&im->qepio.ioport[3].dir1, 0xFDD20800); + out_be32(&im->qepio.ioport[3].dir2, 0x54155228); + out_be32(&im->qepio.ioport[3].ppar1, 0x54A30C00); + out_be32(&im->qepio.ioport[3].ppar2, 0x00000100); +} + +void iop_setup_mcr(void) +{ + immap_t __iomem *im = (immap_t *)CONFIG_SYS_IMMR; + + /* PORTA configuration */ + out_be32(&im->qepio.ioport[0].pdat, 0x00808004); + out_be32(&im->qepio.ioport[0].podr, 0x00000000); + out_be32(&im->qepio.ioport[0].dir1, 0x40800A68); + out_be32(&im->qepio.ioport[0].dir2, 0x650A0896); + out_be32(&im->qepio.ioport[0].ppar1, 0x40400004); + out_be32(&im->qepio.ioport[0].ppar2, 0x05050444); + + /* PORTB configuration */ + out_be32(&im->qepio.ioport[1].pdat, 0x00008000); + out_be32(&im->qepio.ioport[1].podr, 0x00000004); + out_be32(&im->qepio.ioport[1].dir1, 0x50A08A4A); + out_be32(&im->qepio.ioport[1].dir2, 0x5C0C6890); + out_be32(&im->qepio.ioport[1].ppar1, 0x50504444); + out_be32(&im->qepio.ioport[1].ppar2, 0x08080080); + + /* PORTC configuration */ + out_be32(&im->qepio.ioport[2].pdat, 0x3D000018); + out_be32(&im->qepio.ioport[2].podr, 0x00000400); + out_be32(&im->qepio.ioport[2].dir1, 0x45518000); + out_be32(&im->qepio.ioport[2].dir2, 0xA8129561); + out_be32(&im->qepio.ioport[2].ppar1, 0x80008000); + out_be32(&im->qepio.ioport[2].ppar2, 0x00000000); + + /* PORTD configuration */ + out_be32(&im->qepio.ioport[3].pdat, 0x1000E000); + out_be32(&im->qepio.ioport[3].podr, 0x0000E000); + out_be32(&im->qepio.ioport[3].dir1, 0xFDD20800); + out_be32(&im->qepio.ioport[3].dir2, 0x54155228); + out_be32(&im->qepio.ioport[3].ppar1, 0x54A30C00); + out_be32(&im->qepio.ioport[3].ppar2, 0x00000100); +} + +static void iop_setup_cmpcpro(void) +{ + immap_t __iomem *im = (immap_t *)CONFIG_SYS_IMMR; + + /* PORTA configuration */ + out_be32(&im->qepio.ioport[0].pdat, 0x00000000); + out_be32(&im->qepio.ioport[0].podr, 0x00000000); + out_be32(&im->qepio.ioport[0].dir1, 0x50A84020); + out_be32(&im->qepio.ioport[0].dir2, 0x00000000); + out_be32(&im->qepio.ioport[0].ppar1, 0xF0FCC000); + out_be32(&im->qepio.ioport[0].ppar2, 0x00000000); + + /* PORTB configuration */ + out_be32(&im->qepio.ioport[1].pdat, 0x00000000); + out_be32(&im->qepio.ioport[1].podr, 0x00000000); + out_be32(&im->qepio.ioport[1].dir1, 0x00000000); + out_be32(&im->qepio.ioport[1].dir2, 0x00006800); + out_be32(&im->qepio.ioport[1].ppar1, 0x00000000); + out_be32(&im->qepio.ioport[1].ppar2, 0x00000000); + + /* PORTC configuration */ + out_be32(&im->qepio.ioport[2].pdat, 0x19000000); + out_be32(&im->qepio.ioport[2].podr, 0x00000000); + out_be32(&im->qepio.ioport[2].dir1, 0x01410000); + out_be32(&im->qepio.ioport[2].dir2, 0xA8009400); + out_be32(&im->qepio.ioport[2].ppar1, 0x00000000); + out_be32(&im->qepio.ioport[2].ppar2, 0x00000000); + + /* PORTD configuration */ + out_be32(&im->qepio.ioport[3].pdat, 0x1000E000); + out_be32(&im->qepio.ioport[3].podr, 0x0000E000); + out_be32(&im->qepio.ioport[3].dir1, 0xFD020000); + out_be32(&im->qepio.ioport[3].dir2, 0x54055000); + out_be32(&im->qepio.ioport[3].ppar1, 0x54030000); + out_be32(&im->qepio.ioport[3].ppar2, 0x00000000); +} + +int board_early_init_r(void) +{ + immap_t __iomem *im = (immap_t *)CONFIG_SYS_IMMR; + fsl_lbc_t *lbus = &im->im_lbc; + + upmconfig(UPMA, upma_table, ARRAY_SIZE(upma_table)); + + out_be32(&lbus->mamr, 0x00044440); + + /* configure LBCR register */ + out_be32(&lbus->lbcr, 0x00000500); + sync(); + + if (in_8(ADDR_FPGA_REG_ETAT) & R_ETAT_PRES_BASE) { + int i; + + /* Initialize signal PROG_FPGA_FIRMWARE */ + setbits_be32(&im->qepio.ioport[0].pdat, 0x00008000); + setbits_be32(&im->qepio.ioport[0].dir2, 0x60000002); + setbits_be32(&im->qepio.ioport[0].podr, 0x00008000); + + mdelay(1); + + /* Now read CPDATA[31] to check if FPGA is loaded */ + if (!in_be32(&im->qepio.ioport[0].pdat) & 0x00000001) { + printf("Reloading FPGA firmware.\n"); + + clrbits_be32(&im->qepio.ioport[0].pdat, 0x00008000); + udelay(1); + setbits_be32(&im->qepio.ioport[0].pdat, 0x00008000); + + /* Wait 200 msec and check DONE_FPGA_FIRMWARE */ + mdelay(200); + if (!(in_be32(&im->qepio.ioport[0].pdat) & 0x00000001)) { + for (;;) { + printf("error loading firmware.\n"); + mdelay(500); + } + } + + /* Send a reset signal and wait for 20 msec */ + out_8(ADDR_FPGA_RESET_G, in_8(ADDR_FPGA_RESET_G) | RESET_G_OK); + mdelay(20); + out_8(ADDR_FPGA_RESET_G, in_8(ADDR_FPGA_RESET_G) & ~RESET_G_OK); + } + + /* Wait 300 msec and check the reset state */ + mdelay(300); + for (i = 0; !(in_8(ADDR_FPGA_REG_ETAT) & RESET_G_OK); i++) { + for (;;) { + printf("Could not reset FPGA.\n"); + mdelay(500); + } + } + + iop_setup_common(); + + /* clocks configuration */ + out_be32(&qe_immr->qmx.cmxsi1cr_l, 0x00040004); + out_be32(&qe_immr->qmx.cmxsi1syr, 0x00000000); + } else { + iop_setup_cmpcpro(); + } + + return 0; +} + +int dram_init(int board_type) +{ + immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; + + out_be32(&im->sysconf.ddrlaw[0].bar, CFG_SYS_DDR_SDRAM_BASE & LAWBAR_BAR); + out_be32(&im->sysconf.ddrlaw[0].ar, LAWAR_EN | ((ilog2(SZ_512M) - 1) & LAWAR_SIZE)); + + out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_CLK_CNTL); + out_be32(&im->ddr.csbnds[0].csbnds, CFG_SYS_DDR_CS0_BNDS); + out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG); + + out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0); + out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG); + out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2); + out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2); + out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL); + udelay(200); + + setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); + + gd->ram_size = SZ_512M; + + return 0; +} + +int checkboard(void) +{ + printf("Board: "); + + /* Is a motherboard present ? */ + if (in_8(ADDR_FPGA_REG_ETAT) & R_ETAT_PRES_BASE) + return checkboard_common(); + + printf("CMPCPRO (CS GROUP)\n"); + + return 0; +} + +/* Reads MAC addresses from SPI EEPROM */ +static int setup_mac(void) +{ + uchar din[MAX_SPI_BYTES]; + int ret; + unsigned long ident = 0x08005120; + + ret = read_eeprom(din, sizeof(din)); + if (ret) + return ret; + + if (memcmp(din + EE_OFF_MAC1, &ident, sizeof(ident)) == 0) { + eth_env_set_enetaddr("ethaddr", din + EE_OFF_MAC1); + eth_env_set_enetaddr("eth3addr", din + EE_OFF_MAC1); + } + + if (memcmp(din + EE_OFF_MAC2, &ident, sizeof(ident)) == 0) + eth_env_set_enetaddr("eth1addr", din + EE_OFF_MAC2); + + if (memcmp(din + EE_OFF_MAC3, &ident, sizeof(ident)) == 0) + eth_env_set_enetaddr("eth2addr", din + EE_OFF_MAC3); + + return 0; +} + +int misc_init_r(void) +{ + /* we do not modify environment variable area if CRC is false */ + /* Verify if mother board is present */ + if (in_8(ADDR_FPGA_REG_ETAT) & R_ETAT_PRES_BASE) { + misc_init_r_common(); + } else { + env_set("config", CFG_BOARD_CMPCXXX); + env_set("hostname", CFG_BOARD_CMPCXXX); + } + + if (setup_mac()) + printf("Error retrieving mac addresses\n"); + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + ft_cpu_setup(blob, bd); + + /* MIAE only */ + if (!(in_8(ADDR_FPGA_REG_ETAT) & R_ETAT_PRES_BASE)) + return 0; + + return ft_board_setup_common(blob); +} + +void ft_board_setup_phy3(void) +{ + /* switch to phy3 with gpio, we'll only use phy3 */ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + setbits_be32(&immr->qepio.ioport[2].pdat, 0x00000400); +} + +#define ADDR_FPGA_R_BASE ((unsigned char __iomem *)CONFIG_FPGA_BASE) +#define ADDR_FPGA_R_ALARMES_IN ((unsigned char __iomem *)CONFIG_FPGA_BASE + 0x31) +#define ADDR_FPGA_R_FAV ((unsigned char __iomem *)CONFIG_FPGA_BASE + 0x44) + diff --git a/board/cssi/cmpcpro/cmpcpro.env b/board/cssi/cmpcpro/cmpcpro.env new file mode 100644 index 0000000000..7394b8386e --- /dev/null +++ b/board/cssi/cmpcpro/cmpcpro.env @@ -0,0 +1,8 @@ +loadaddr=0x1a00000 +filename=cmpcpro.itb +netdev=eth0 +console_args=console=ttyS0,115200N8 +loadkernel=ubi part nand0;ubifsmount ubi0; ubifsload ${loadaddr} /boot/${filename}; ubifsumount; ubi detach +flashboot=mw.w 90000040 0x000E 1; setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; run loadkernel; bootm $loadaddr#$config +tftpboot=mw.w 90000040 0x000E 1; setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; tftp ${loadaddr} ${filename}; bootm $loadaddr#$config +update=echo 'Updating ubi image'; mw.w 90000040 0x000E 1; if tftp $loadaddr $ubifile; then nand erase.chip; nand write $loadaddr 0x00 $filesize; fi; diff --git a/board/cssi/cmpcpro/nand.c b/board/cssi/cmpcpro/nand.c new file mode 100644 index 0000000000..d8b4197314 --- /dev/null +++ b/board/cssi/cmpcpro/nand.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2010-2023 CS GROUP France + * Florent TRINH THAI (florent.trinh-thai@csgroup.eu) + * Stephane FRANJOU (stephane.franjou@csgroup.eu) + */ + +#include +#include +#include +#include +#include + +#define BIT_CLE BIT(6) +#define BIT_ALE BIT(5) + +static u32 nand_mask(unsigned int ctrl) +{ + return ((ctrl & NAND_CLE) ? BIT_CLE : 0) | + ((ctrl & NAND_ALE) ? BIT_ALE : 0); +} + +static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) +{ + immap_t __iomem *immr = (immap_t *)CONFIG_SYS_IMMR; + struct nand_chip *chip = mtd_to_nand(mtdinfo); + + if (ctrl & NAND_CTRL_CHANGE) + clrsetbits_be32(&immr->qepio.ioport[2].pdat, + BIT_CLE | BIT_ALE, nand_mask(ctrl)); + + if (cmd != NAND_CMD_NONE) + out_8(chip->IO_ADDR_W, cmd); +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->chip_delay = 60; + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = nand_hwcontrol; + + return 0; +} diff --git a/configs/CMPCPRO_defconfig b/configs/CMPCPRO_defconfig new file mode 100644 index 0000000000..7313715624 --- /dev/null +++ b/configs/CMPCPRO_defconfig @@ -0,0 +1,209 @@ +CONFIG_PPC=y +CONFIG_SYS_IMMR=0xB0000000 +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="cmpcpro" +CONFIG_SYS_PROMPT="MPC_PRO> " +CONFIG_SYS_CLK_FREQ=66666667 +CONFIG_ENV_ADDR=0x400e0000 +CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y +CONFIG_TARGET_CMPCPRO=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="FLASH" +CONFIG_BAT0_BASE=0x40000000 +CONFIG_BAT0_LENGTH_64_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_WRITETHROUGH=y +CONFIG_BAT0_DCACHE_WRITETHROUGH=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="DDR" +CONFIG_BAT1_BASE=0x00000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="DDR2" +CONFIG_BAT2_BASE=0x10000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="BCSR" +CONFIG_BAT3_BASE=0xA0000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_GUARDED=y +CONFIG_BAT3_DCACHE_WRITETHROUGH=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="PERIPHETH" +CONFIG_BAT4_BASE=0x90000000 +CONFIG_BAT4_LENGTH_64_MBYTES=y +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_ICACHE_GUARDED=y +CONFIG_BAT4_DCACHE_WRITETHROUGH=y +CONFIG_BAT4_DCACHE_INHIBITED=y +CONFIG_BAT4_DCACHE_GUARDED=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="CARTEBASE" +CONFIG_BAT5_BASE=0x80000000 +CONFIG_BAT5_LENGTH_64_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_WRITETHROUGH=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="IMMRBAR" +CONFIG_BAT6_BASE=0xB0000000 +CONFIG_BAT6_LENGTH_4_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_BAT7=y +CONFIG_BAT7_NAME="STACK" +CONFIG_BAT7_BASE=0xE6000000 +CONFIG_BAT7_ACCESS_RW=y +CONFIG_BAT7_USER_MODE_VALID=y +CONFIG_BAT7_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0x40000000 +CONFIG_LBLAW0_LENGTH_64_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xA0000000 +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0x90000000 +CONFIG_LBLAW2_LENGTH_64_MBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0x80000000 +CONFIG_LBLAW3_LENGTH_64_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_IFEB=y +CONFIG_HID2_EBPX=y +CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_3=y +CONFIG_ACR_RPTCNT_3=y +CONFIG_SPCR_OPT_SPEC_READ=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y +CONFIG_SYS_MONITOR_LEN=393216 +CONFIG_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=5 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_FLUSH_STDIN=y +CONFIG_AUTOBOOT_PROMPT="\nEnter password - autoboot in %d sec...\n" +CONFIG_AUTOBOOT_ENCRYPTION=y +CONFIG_AUTOBOOT_STOP_STR_ENABLE=y +CONFIG_AUTOBOOT_STOP_STR_SHA256="4813494d137e1631bba301d5acab6e7bb7aa74ce1185d456565ef51d737677b2" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run flashboot" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_MISC_INIT_R=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x10000000 +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y +CONFIG_CMD_DHCP=y +CONFIG_BOOTP_BOOTFILESIZE=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +# CONFIG_CMD_SLEEP is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="UEC0" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="cmpcpro" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.0.3" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.0.1" +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_CLK=y +CONFIG_CPU=y +CONFIG_CPU_MPC83XX=y +CONFIG_SYS_BR0_PRELIM_BOOL=y +CONFIG_SYS_BR0_PRELIM=0x40001001 +CONFIG_SYS_OR0_PRELIM=0xFC001080 +CONFIG_SYS_BR1_PRELIM_BOOL=y +CONFIG_SYS_BR1_PRELIM=0xA0000801 +CONFIG_SYS_OR1_PRELIM=0xFFFF9030 +CONFIG_SYS_BR2_PRELIM_BOOL=y +CONFIG_SYS_BR2_PRELIM=0x90001001 +CONFIG_SYS_OR2_PRELIM=0xfc001090 +CONFIG_SYS_BR3_PRELIM_BOOL=y +CONFIG_SYS_BR3_PRELIM=0x80001081 +CONFIG_SYS_OR3_PRELIM=0xfc000100 +CONFIG_MPC8XXX_GPIO=y +CONFIG_QE_GPIO=y +# CONFIG_I2C is not set +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_MII=y +CONFIG_RMII=y +CONFIG_QE_UEC=y +CONFIG_QE=y +CONFIG_U_QE=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MPC8XXX_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_MPC83XX=y +CONFIG_WDT=y +CONFIG_WDT_MPC8xxx=y +# CONFIG_REGEX is not set +CONFIG_LZMA=y diff --git a/include/configs/cmpcpro.h b/include/configs/cmpcpro.h new file mode 100644 index 0000000000..24e62dfcf0 --- /dev/null +++ b/include/configs/cmpcpro.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006-2023 CS GROUP France + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * System IO Config + */ +#define CFG_SYS_SICRL 0x00000000 + +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 + +#define CFG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ + +/* + * Manually set up DDR parameters + */ + +/* DDR 512 M */ +#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_CFG | CSCONFIG_BANK_BIT_3 | \ + CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10) +/* 0x80840102 */ +#define CFG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_MRS_CYC_SHIFT)) +/* 0x00220802 */ +#define CFG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) | \ + (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (5 << TIMING_CFG1_CASLAT_SHIFT) | \ + (27 << TIMING_CFG1_REFREC_SHIFT) | \ + (2 << TIMING_CFG1_WRREC_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT)) +/* 0x3935D322 */ +#define CFG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (31 << TIMING_CFG2_CPO_SHIFT) | \ + (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) +/* 0x0F9048CA */ +#define CFG_SYS_DDR_TIMING_3 0x00000000 +#define CFG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +/* 0x02000000 */ +#define CFG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) | (0x0232 << SDRAM_MODE_SD_SHIFT)) +/* 0x44400232 */ +#define CFG_SYS_DDR_MODE2 0x8000c000 +#define CFG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) | \ + (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) +#define CFG_SYS_DDR_CS0_BNDS (CFG_SYS_DDR_SDRAM_BASE >> 8 | 0x0000001F) + +#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_32_BE) +/* 0x43080000 */ +#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000 + +/* + * Initial RAM Base Address Setup + */ +#define CFG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x110000) +#define CFG_SYS_INIT_RAM_SIZE 0x4000 + +/* + * FLASH on the Local Bus + */ +#define CFG_SYS_FLASH_BASE 0x40000000 /* FLASH base address */ +#define CFG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */ + +/* + * NAND + */ +#define CFG_SYS_NAND_BASE 0xa0000000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ SZ_256M + +/* Board names */ +#define CFG_BOARD_CMPCXXX "cmpcpro" +#define CFG_BOARD_MCR3000_2G "mcrpro" +#define CFG_BOARD_VGOIP "vgoippro" +#define CFG_BOARD_MIAE "miaepro" + +#endif /* __CONFIG_H */ -- 2.39.5