From 485e822346caa982a5c17b7b136b17e8d09dafee Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 12 Dec 2018 06:12:40 -0800
Subject: [PATCH] riscv: Do some basic architecture level cpu initialization

In arch_cpu_init_dm() do some basic architecture level cpu
initialization, like FPU enable, etc.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/cpu/cpu.c | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index fc7c9b3751..e662140427 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -8,6 +8,7 @@
 #include <dm.h>
 #include <log.h>
 #include <asm/csr.h>
+#include <asm/encoding.h>
 #include <dm/uclass-internal.h>
 
 /*
@@ -61,7 +62,31 @@ static int riscv_cpu_probe(void)
 
 int arch_cpu_init_dm(void)
 {
-	return riscv_cpu_probe();
+	int ret;
+
+	ret = riscv_cpu_probe();
+	if (ret)
+		return ret;
+
+	/* Enable FPU */
+	if (supports_extension('d') || supports_extension('f')) {
+		csr_set(MODE_PREFIX(status), MSTATUS_FS);
+		csr_write(fcsr, 0);
+	}
+
+	if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
+		/*
+		 * Enable perf counters for cycle, time,
+		 * and instret counters only
+		 */
+		csr_write(mcounteren, GENMASK(2, 0));
+
+		/* Disable paging */
+		if (supports_extension('s'))
+			csr_write(satp, 0);
+	}
+
+	return 0;
 }
 
 int arch_early_init_r(void)
-- 
2.39.5