From 3cf97f4543f34e7be3f2a3cc15bef5243eb822f9 Mon Sep 17 00:00:00 2001
From: Ajay Bhargav <[ajay.bhargav@einfochips.com]>
Date: Mon, 22 Aug 2011 17:57:38 +0530
Subject: [PATCH] gpio: Add GPIO driver for Marvell SoC Armada100
This patch adds support for generic GPIO driver framework for Marvell
SoC Armada100.
Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
---
arch/arm/include/asm/arch-armada100/gpio.h | 48 ++++++++++++++++++++++
1 file changed, 48 insertions(+)
create mode 100644 arch/arm/include/asm/arch-armada100/gpio.h
diff --git a/arch/arm/include/asm/arch-armada100/gpio.h b/arch/arm/include/asm/arch-armada100/gpio.h
new file mode 100644
index 0000000000..9e5e7b9b11
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/gpio.h
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_GPIO_H
+#define _ASM_ARCH_GPIO_H
+
+#include <asm/types.h>
+#include <asm/arch/armada100.h>
+
+#define GPIO_HIGH 1
+#define GPIO_LOW 0
+
+#define GPIO_TO_REG(gp) (gp >> 5)
+#define GPIO_TO_BIT(gp) (1 << (gp & 0x1F))
+#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01)
+
+static inline void *get_gpio_base(int bank)
+{
+ const unsigned int offset[4] = {0, 4, 8, 0x100};
+ /* gpio register bank offset - refer Appendix A.36 */
+ return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]);
+}
+
+#endif /* _ASM_ARCH_GPIO_H */
--
2.39.5