From 0b0d433b6c73fafc448c02b75196391ab3031a84 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 15 Jun 2022 11:56:54 +0200 Subject: [PATCH] arm64: zynqmp: Fix i2c addresses for vck190 SC si570 is normally at 0x5d address and address is not aligned with address in node. 8T49N240 can't be at 0xd8 that's why it is shifter by one bit. Signed-off-by: Michal Simek Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/4fa86fffa9cb8abe633fbc5a9c55bea249b5edfb.1655287013.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 7261837823..37c56181c9 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -294,10 +294,10 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */ + clock_8t49n287: clock-generator@6c { /* u39 8T49N240 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ - reg = <0xd8>; + reg = <0x6c>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; @@ -447,7 +447,7 @@ si570_user1: clock-generator@5d { /* u205 */ #clock-cells = <0>; compatible = "silabs,si570"; - reg = <0x5f>; + reg = <0x5d>; temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; -- 2.39.5