Marek Vasut [Tue, 12 Apr 2022 15:26:01 +0000 (17:26 +0200)]
ARM: dts: imx: Add support for Data Modul i.MX8M Mini eDM SBC
Add support for Data Modul i.MX8M Mini eDM SBC board. This is an
evaluation board for various custom display units. Currently
supported are serial console, ethernet, eMMC, SD, SPI NOR,
USB host and USB OTG.
Reviewed-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
iopoll: Extend read_poll_timeout macro to support variable parameters
This macro currently supports only one parameter. Based on Linux iopoll,
let's extend read_poll_timeout common API to allow multiple variable
parameters.
phy: nxp-c45-tja11xx: Rename functions to be c45 tja11xx specific
This driver supports NXP C45 TJA11XX PHYs, but there're also other NXP
TJA11XX PHYs. Let's rename functions in this driver to be c45 variant
specific, so further drivers can be introduced adding support for NXP
TJA11XX PHYs.
Peng Fan [Sun, 10 Apr 2022 04:18:27 +0000 (12:18 +0800)]
imx8mq: soc: Set the BYPASS ID SWAP bit (GPR10 bit 1)
Set the BYPASS ID SWAP bit (GPR10 bit 1).
The ID SWAP function randomly make TZASC grant non-secure access to
secure memory. TZASC ID SWAP should be bypassed by setting the bit
TZASC_ID_SWAP_BYPASS(bit 1) in IOMUX_GPR10 register.
Turns out on certain carrier boards (e.g. Iris V2) and under certain
circumstances (e.g. after a software reset) the SD card may have been
left in a strange state which later failed as follows:
Colibri iMX6ULL # mmc dev 0
Card did not respond to voltage select! : -110
Fix this as follows:
- Re-name the signaling voltage rail regulator from vmmc to vqmmc.
- Fix the name of the GPIO property to gpios.
- Specify 4-bit bus width, no write-protect capability and no 1.8
volt signaling voltage capability.
- Fix the clock vs. command pull-up vs. push-pull configuration.
Now that it is possible to use regulator-fixed-clock make use
of it. This makes U-Boot detect the PHY on first cold-boot.
This commit also adjusts the code in setup_fec and follows
how it is done in mx6ullevk.c
This commit also slows down the boot-process by about 150ms
as it now waits for the regulator-fixed-clock voltage that
drives the PHY to go up.
If you rely on very fast boot-speeds and don't need ethernet
for your boot-process you can safely revert the changes on
imx6ull-colibri.dtsi
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
board: colibri-imx6ull: Do not leave variant variable unset
Toradex uses the variable variant to distinguish between modules with
eMMC, NAND with wifi and NAND without wifi.
This variable is set on every boot. Set this variable also if we have a
NAND module without wifi to prevent issues.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Rename board_early_init_f() to board_early_init(), since this function
has nothing to do with actual board_early_init_f() as used throughout
U-Boot. The board_early_init() is function local to this board used to
configure UART and WDT pinmux. Wrap init_uart_clk() into this function
so that early UART init would be all in one place. Turn the function
into __weak one, so it could be overridden in case custom carrier board
uses different UART or needs custom IOMUX settings.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Max Krummenacher <max.krummenacher@toradex.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
Ye Li [Thu, 7 Apr 2022 07:55:56 +0000 (15:55 +0800)]
imx8m: soc: Relocate u-boot to the top DDR in 4GB space
The EFI memory init uses gd->ram_top for conventional memory. In
current implementation, the ram_top is below optee address. This cause
grub failed to allocation memory for initrd.
The change updates DDR bank setup functions to place the u-boot at top
DDR in 4GB space.
Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 7 Apr 2022 07:55:54 +0000 (15:55 +0800)]
imx: imx8m: soc: runtime drop extcon property from usbotg node
The extcon is an decrepted property and not used by upstream Linux and
NXP 5.10 kernel, so we remove it before kicking linux in case it is in
dts. Otherwise distro kernel will not able to have usb function.
Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 7 Apr 2022 07:55:53 +0000 (15:55 +0800)]
imx: imx8mp: disable fused IP for UltraLite
Beside the fused modules on iMX8MP Lite, this part has also fused
GPU3D/2D, LVDS and MIPI DSI.
So we have to disable them for kernel and also disable MIPI DSI
in u-boot DTS for splash screen at runtime.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Wait 1ms before issuing the first MRS command to write DDR3 Mode
registers.
There is a requirement to wait a minimum time before issuing command to
the DDR3 device, according to the JEDEC standard this time is 500us
(after RESET_n is de-asserted until CKE becomes active) + tXPR (Reset
CKE Exit time, maximum value 360ns).
It seems that for some reason this is not enforced by the MMDC
controller.
Without this change we experienced random memory initialization failures
with about 2% boot failure rate on specific problematic boards, after
this change we were able to do more than 10.000 power-cycle without a
single failure.
Fixes: fe0f7f7842e1 ("mx6: add mmdc configuration for MX6Q/MX6DL") Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
mx6: ddr: Restore ralat/walat in write level calibration
The current DDR write level calibration routine always overwrite
the ralat/walat fields to their maximum value, just save
the existing values at the beginning of the calibration routine
and restore it at the end.
In case the delay is estimated by the user to be more than one cycle the
walat should be configured according to that, this is not
automatically done. From the i.MX6 RM:
The user should read the results of the associated delay-line at
MPWLDECTRL#[WL_DL_ABS_OFFSET#] and in case the user estimates that the
reasonable delay may be above 1 cycle then the user should indicate it at
MPWLDECTRL#[WL_CYC_DEL#]. Moreover the user should indicate it in
MDMISC[WALAT] field. For example, if the result of the write leveling calibration
is 100/256 parts of a cycle, but the user estimates that the delay is above 2 cycles
then MPWLDECTRL#[WL_CYC_DEL#] should be configured to 2, so the total
delay will be 2 and 100/256 parts of a cycle
Probably it would just possible to not overwrite the mdmisc register in
the first place, since this is not present in the write_level_calib() example
in NXP AN4467 nor in the i.MX6 RM (44.11.6.1 Hardware Write Leveling
Calibration).
Fixes: d339f16911c7 ("arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL") Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
Peng Fan [Wed, 6 Apr 2022 06:30:31 +0000 (14:30 +0800)]
misc: imx8ulp: Update fuse driver
- According to S400 API, the fuse bank 25 (Testconfig2) is able to
access. Add it into driver's mapping table.
- According to FSB words list, the reserved 48 words are ahead of
the bank 5 and bank 6. Fix the wrong position.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Wed, 6 Apr 2022 06:30:27 +0000 (14:30 +0800)]
imx: imx8ulp: enable wdog_ad interrupt in CMC1
Enable wdog_ad interrupt being triggered by CMC1 to CM33 to let CM33
know A35 reset and reinitialize rpmsg.
Clear wdog_ad and AD_PERIPH reset interrupt after A35 up, otherwise
M33 will always receive interrupt.
Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 6 Apr 2022 06:30:23 +0000 (14:30 +0800)]
imx: imx8ulp_evk: call the handshake with M33
If M33 handshake is successful, TPM and DSI panel MUX setting is
done by M33, no need to set them.
If handshake is failed or M33 is not booted, continue the TPM
and DSI panel MUX setting
Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 6 Apr 2022 06:30:17 +0000 (14:30 +0800)]
imx: imx8ulp: Change LPAV assignment for dual boot
Assign the LPAV owner to RTD, and assign LPAV masters and peripherals
to APD. So except the masters and peripherals, other resources
(like DDR, cgc2, pcc5) in LPAV won't be reset during reboot and suspend.
No needs to initialize DDR again after reboot.
Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Wed, 6 Apr 2022 06:30:15 +0000 (14:30 +0800)]
imx: imx8ulp: enable MU0_B clk by default
Enable MU0_B clk by default. When M33 image is loaded by Jlink,
the previous method not enable MU0_B clk and not able to communicate
with M33, so let's enable it by default.
And we not put it under kernel dts, because it conflicts with i.MX8QM
suspend/resume logic which requires large change.
Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 6 Apr 2022 06:30:14 +0000 (14:30 +0800)]
imx: imx8ulp: cgc: Switch to NICLPAV to FRO192 before PLL4 init
When reset with dual boot mode, the LPAV domain won't power down
due to its master is not assigned to APD. So the NICLPAV keeps the
last setting to use PLL4PFD1. So before SPL initialize the PLL4,
we need to switch NICLPAV to FRO192, otherwise system will hang.
Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 6 Apr 2022 06:30:13 +0000 (14:30 +0800)]
imx: imx8ulp_evk: Skip init DDR for reboot in dual boot mode
When M33 is LPAV owner in dual boot, DDR, PCC5, CGC2 won't be reset
during APD reset. So no need to init DDR again after reboot, but need to
reconfigure the PLL4 PFD/PFDDIV/LPAV NIC etc, because kernel may
change or disable some of them.
Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Wed, 6 Apr 2022 06:30:12 +0000 (14:30 +0800)]
imx: imx8ulp: add ND/LD clock
Add a new ddr script, defconfig for ND
Configure the clock for ND mode
changing A35 to 960MHz for OD mode
Update NIC CLK for the various modes
Introduce clock_init_early/late, late is used after pmic voltage
setting, early is used in the very early stage for upower mu, lpuart and
etc.
Note: NIC runs at 324MHz, 442MHz has some random kernel hang issue with
cpuidle enabled now.
Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
This workaround is not needed on i.MX8ULP proto-1B EVK as board has
fixed the problem. Because we don't support proto-1A any longer,
remove the PMIC settings.
Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 6 Apr 2022 06:30:08 +0000 (14:30 +0800)]
imx: imx8ulp: Add M33 handshake functions
Add functions to check if M33 image is booted and handshake with M33
image via MU. A core notifies M33 to start init by FCR F0, then wait
M33 init done signal by checking FSR F0.
Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 6 Apr 2022 06:30:06 +0000 (14:30 +0800)]
imx: imx8ulp: Set COUNTER_FREQUENCY to 1Mhz
The COUNTER_FREQUENCY is missed in 8ulp configs, it will cause SPL
and u-boot not set the cntfrq_el0. For u-boot, this is ok, because
ATF has set it. But for SPL, it will lead delay and get_timer
not working.
Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Mon, 28 Mar 2022 09:14:07 +0000 (17:14 +0800)]
mtd: nand: mxs_nand_spl: Remove the page aligned access
The mxs_nand_spl driver can support to read from page unaligned offset,
so don't need to set bl_len to ask spl_load_simple_fit to handle
the page unaligned access.
Actually spl_load_simple_fit has two parts of reading:
spl_simple_fit_read and spl_load_fit_image.
The spl_load_fit_image can handle the page unaligned offset,
but the spl_simple_fit_read can't do it. spl_simple_fit_read requires
the FIT location at page aligned offset.
Hence, remove the nand_get_mtd overwrite function from mxs_nand_spl
to use page unaligned read by driver.
Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Tim Harvey <tharvey@gateworks.com> #gw_ventana
Marek Vasut [Fri, 25 Mar 2022 17:59:28 +0000 (18:59 +0100)]
ARM: imx: Decode ECSPI env location from i.MX8M ROMAPI tables
Decode ECSPI boot device in env_get_location() from i.MX8M ROMAPI tables.
This is necessary to correctly identify env is in SPI NOR when the system
boots from SPI NOR attached to ECSPI.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
Because the Beacon imx8mn board uses device tree
for MMC/SD and Ethernet, there is no need to have some of the
config options. It's handled by the device tree.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Because the Beacon imx8mm board uses device tree
for MMC/SD and Ethernet, there is no need to have some of the
config options. It's handled by the device tree.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Fabio Estevam [Tue, 15 Mar 2022 20:47:05 +0000 (17:47 -0300)]
tbs2910: Convert to DM_SERIAL
Conversion to DM_SERIAL is mandatory.
Select DM_SERIAL and add a imx6q-tbs2910-u-boot.dtsi file
that describes the nodes that require dm-pre-reloc, which allows
the DM model to configure the UART pinctrl early.
Remove the now unneeded board UART initialization.
Tim Harvey [Tue, 8 Mar 2022 00:24:04 +0000 (16:24 -0800)]
drivers: misc: add Gateworks System Controller driver
Add a driver for the Gateworks System Controller used on Gateworks boards
which provides a boot watchdog, power control, temperature monitor,
and voltage ADCs.
Tim Harvey [Tue, 8 Mar 2022 00:24:03 +0000 (16:24 -0800)]
board: gateworks: gw_ventana: move ft_early_fixups out of common
DM is not used for the SPL and a generic DT is used in the SPL
which requires no fixups. Remove the call in the SPL and move the function
into the U-Boot code.
Tim Harvey [Tue, 8 Mar 2022 00:24:01 +0000 (16:24 -0800)]
board: gateworks: gw_ventana: move SPL uart config out of common
Since DM_SERIAL is used for U-Boot we no longer need legacy UART code in
common.c shared by the SPL and U-Boot. Move the legacy UART config to
the non-DM SPL.
Tim Harvey [Tue, 8 Mar 2022 00:24:00 +0000 (16:24 -0800)]
board: gateworks: gw_ventana: convert to DM_I2C
convert to DM_I2C for U-Boot while leaving SPL legacy I2C:
- Move I2C config from common to SPL
- Move PMIC config from common to SPL (no need to re-configure pmic)
- add DM_I2C support to eeprom/gsc functions shared by SPL and U-Boot
Heiko Thiery [Sat, 26 Feb 2022 09:44:21 +0000 (10:44 +0100)]
ARM: imx: imx8mn-evk: enable DM_SERIAL
U-Boot complains that CONFIG_SERIAL is not converted to CONFIG_DM_SERIAL
and gives a deadline before possibly removing the board. Migrate to
DM_SERIAL to fulfill the request.
Marek Vasut [Sat, 26 Feb 2022 03:37:08 +0000 (04:37 +0100)]
pmic: pca9450: Add PCA9450C compatible string
Add DT compatible string for PCA9450C PMIC. This is a variant of the
PCA9450 PMIC with 6 A dual-phase buck regulator and 3 A buck regulator,
and is software-wise compatible with the PCA9450B. This variant of the
PCA9450 is designed for use as companion PMIC for i.MX8MP.
The correct compatible string for i.MX8MP variant of DWC EQoS MAC
is "nxp,imx8mp-dwmac-eqos", use it. Drop the two current users of
the current wrong compatible string to avoid breaking them.
Adam Ford [Wed, 23 Feb 2022 13:50:51 +0000 (07:50 -0600)]
imx: imx8mm/imx8mn_beacon: Remove redundant code
The Ethernet controller and PHY use the device tree info to
configure themselves, so it's not necessary to manually do it
in the board file. This permits the removal of a bunch of headers
as well.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Acked-by: Peng Fan <peng.fan@nxp.com>
Heiko Thiery [Wed, 23 Feb 2022 09:48:26 +0000 (10:48 +0100)]
ARM: imx: imx8mn-*-evk: use reset-gpios in phy node
To be in sync with the linux devicetree change the 'phy-reset-gpios' in
the fec node to 'reset-gpios' in the phy node. The PHY reset will be
done by the eth-phy-uclass driver while probing the PHY. This is ok
since it is done before probing the fec.
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