Philippe Reynes [Fri, 18 Sep 2020 12:13:00 +0000 (14:13 +0200)]
net: add a generic udp protocol
This commit adds a generic udp protocol framework in the
network loop. So protocol based on udp may be implemented
without modifying the network loop (for example custom
wait magic packet).
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Ley Foon Tan [Tue, 25 Aug 2020 02:26:36 +0000 (10:26 +0800)]
net: tftp: Fix store_block offset calculation
tftp_cur_block start with 1 for first block, but tftp_cur_block counter is
start with zero when block number is rollover. The existing code
"tftp_cur_block - 1" will cause the block number become -1 in store_block()
when tftp_cur_block is 0 when tftp_cur_block is rollover.
The fix pass in tftp_cur_block to store_block() and minus the
tftp_block_size when do the offset calculation.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
Ley Foon Tan [Tue, 25 Aug 2020 02:26:35 +0000 (10:26 +0800)]
net: tftp: Fix tftp_prev_block counter update
Fixes missing update to tftp_prev_block counter before increase
tftp_cur_block counter when do the tftpput operation.
tftp_prev_block counter is used in update_block_number() function to
check whether block number (sequence number) is rollover. This bug
cause the tftpput command fail to upload a large file when block
number is greater than 16-bit (0xFFFF).
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
net: ftgmac100: Add support for board specific PHY interface address
ftgmac100 driver is using hard-coded PHY interface address of zero.
Each board can have different PHY interface address (phy_addr).
This commit modifies the driver to make use of board specific address
by leveraging CONFIG_PHY_ADDR.
Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
Heiko Stuebner [Tue, 9 Jun 2020 13:37:40 +0000 (15:37 +0200)]
net: phy: mscc: sync rx/tx delay settings with Linux on vsc85xx
The Linux kernel does set the clock delays to
- 0.2 ns (their default, and lowest, hardware value) if delays should
not be enabled
- 2.0 ns (which causes the data to be sampled at exactly half way between
clock transitions at 1000 Mbps) if delays should be enabled
depending on the interface mode
See https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/phy/mscc/mscc_main.c#n523
So instead of using arbitrary delay values like now, mimic this behaviour.
The behaviour is the same for all of vsc8530/8531/8540/8541 so move that
to a shared function while at it.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Heiko Stuebner [Tue, 9 Jun 2020 13:37:39 +0000 (15:37 +0200)]
net: phy: mscc: make clock-output configurable on vsc85xx
The vsc8530/8531/8540/8541 phys have a configurable clock output that
can emit 25, 50 and 125 MHz rates, which in turn may be needed for
stable network connections.
This follows a similar change introduced into the Linux kernel at
https://lore.kernel.org/netdev/20200609133140.1421109-2-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tom Rini [Wed, 30 Sep 2020 13:21:43 +0000 (09:21 -0400)]
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv into next
- Disable CMD_IRQ for RISC-V.
- Update sipeed/maix doc
- Obtain reg of SiFive RAM via dev_read_addr_index() instead of regmap API.
- Cleans up RISC-V timer drivers and converts them to DM.
- Correctly handle IPIs already pending upon prior stage bootloader (on the K210)
Sean Anderson [Tue, 15 Sep 2020 14:45:22 +0000 (10:45 -0400)]
dm: Print device name in dev_xxx like Linux
This adorns messages generated by dev_xxx with the device and driver
names. It also redirects dev_xxx to log when it is available. The names
of these functions very roughly take inspiration from Linux, but there is
no deeper correlation.
Both struct udevice and struct device are supported when logging, though
logging with struct device is no better than using log_xxx. The latter is
supported because of the large amount of existing code which logs with
struct device.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Sean Anderson [Tue, 15 Sep 2020 14:45:20 +0000 (10:45 -0400)]
video: stm32: Fix not calling dev_xxx with a device
There is no member `dev` in dw_mipi_dsi, but there is one in mipi_dsi_host,
so use that.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Sean Anderson [Tue, 15 Sep 2020 14:45:15 +0000 (10:45 -0400)]
usb: dwc2: Fix not calling dev_xxx with a device
This adds a dev argument to some functions so dev_xxx always has a device
to log with. In one instance we must use use a different log function when
we are compiled without DM_USB.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Sean Anderson [Tue, 15 Sep 2020 14:45:12 +0000 (10:45 -0400)]
spi: zynqmp_gqspi: Fix not calling dev_err with a device
Use `bus` instead of `dev`.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Sean Anderson [Tue, 15 Sep 2020 14:45:06 +0000 (10:45 -0400)]
phy: usbphyc: Fix not calling dev_err with a device
Use the phy's device.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Sean Anderson [Tue, 15 Sep 2020 14:45:03 +0000 (10:45 -0400)]
phy: rockchip: Fix not calling dev_err with a device
Get the device from phy, or pass the phy in.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Sean Anderson [Tue, 15 Sep 2020 14:44:57 +0000 (10:44 -0400)]
net: mvpp2: Convert netdev_xxx to dev_xxx
netdev_xxx evaluates to printf in U-Boot, so there is no extra info
printed. mvpp2 one of only two drivers which use these functions in U-Boot.
Convert these functions to dev_xxx where possible (and to log_xxx where
not).
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Sean Anderson [Tue, 15 Sep 2020 14:44:55 +0000 (10:44 -0400)]
net: mvneta: Convert netdev_xxx to dev_xxx
netdev_xxx evaluates to printf in U-Boot, so there is no extra info
printed. mvneta is one of two drivers which use these functions in U-Boot.
Convert these functions to dev_xxx where possible (and to log_xxx where
not).
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Sean Anderson [Tue, 15 Sep 2020 14:44:51 +0000 (10:44 -0400)]
nand: vybrid: Re-introduce vf610_nfc.dev
This member was presumably dropped when this driver was converted from
Linux. However, it is still used in log statements during initialization.
This patch adds the member back. In addition, allocation of struct
vf610_nfc has been moved to the callers of vf610_nfc_nand_init. This allows
it to be allocated by DM (if it is being used) and for dev to be
initialized.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Sean Anderson [Tue, 15 Sep 2020 14:44:50 +0000 (10:44 -0400)]
nand: brcmnand: Fix not calling dev_err() with a device
There are too many levels of indirection when calling dev_err. This is an
artifact of the conversion of brcmnand_host.pdev from a struct
platform_device (which has a member `dev` pointing to a struct device) to
struct udevice.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Sean Anderson [Tue, 15 Sep 2020 14:44:43 +0000 (10:44 -0400)]
mtd: spi: Fix logging in spi-nor-tiny
This fixes dev_xxx() not always being called with a device. In
spi_nor_reg_read, a the slave device may not always be available, so we use
bus and cs instead.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Sean Anderson [Tue, 15 Sep 2020 14:44:41 +0000 (10:44 -0400)]
mtd: nand: sunxi: Fix not calling dev_err with a device
Usually the device is gotten from sunxi_nfc. This is a struct device and
not a struct udevice, but the whole driver seems to be written wihout DM
anyway...
In a few instances, this patch modifies functions to take an nfc to log
with. In once instance we use mtd_info's device since there is no nfc.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Sean Anderson [Tue, 15 Sep 2020 14:44:39 +0000 (10:44 -0400)]
i2c: mxc: Fix dev_err being called on a nonexistant variable
The udevice we are working with is called `bus` and not `dev`.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Sean Anderson [Tue, 15 Sep 2020 14:44:37 +0000 (10:44 -0400)]
dm: syscon: Fix calling dev_dbg with an uninitialized device
We can't use dev_dbg here because we haven't bound to the device yet. Use
log_debug instead.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Sean Anderson [Mon, 21 Sep 2020 11:51:41 +0000 (07:51 -0400)]
riscv: Add some comments to start.S
This adds comments regarding the ordering and purpose of certain
instructions as I understand them.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Liang <ycliang@andestech.com>
Sean Anderson [Mon, 21 Sep 2020 11:51:40 +0000 (07:51 -0400)]
riscv: Ensure gp is NULL or points to valid data
This ensures constructs like `if (gd & gd->...) { ... }` work when
accessing the global data pointer. Without this change, it was possible for
a very early trap to cause _exit_trap to directly or indirectly (through
printf) to read arbitrary memory. This could cause a second trap,
preventing show_regs from being printed.
printf (and specifically puts) uses gd to determine what function to print
with. These functions in turn use gd to find the serial device, etc.
However, before accessing gd, puts first checks to see if it is non-NULL.
This indicates an existing (perhaps undocumented) assumption that either gd
is NULL or it is completely valid.
Before this patch, gd either points to unexpected data (because it retains
the value it did from the prior-stage) or points to uninitialized data
(because it has not yet been initialized by board_init_f_init_reserve)
until the hart has acquired available_harts_lock. This can cause two
problems, depending on the value of gd->flags. If GD_FLG_SERIAL_READY is
unset, then some garbage data will be printed to stdout, but there will not
be a second trap. However, if GD_FLG_SERIAL_READY is set, then puts will
try to print with serial_puts, which will likely cause a second trap.
After this patch, gd is zero up until either a hart has set it in
wait_for_gd_init, or until it is set by arch_init_gd. This prevents its
usage before its data is initialized because both handle_trap and puts
ensure that gd is nonzero before using it. After gd has been set, it is OK
to access it because its data has been cleared (and so flags is valid).
XIP cannot use locks because flash is not writable. This leaves it
vulnerable to the same class of bugs regarding already-pending IPIs as
before this series. Fixing that would require finding another method of
synchronization, which is outside the scope of this series.
Fixes: 7c6ca03eae ("riscv: additional crash information") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
Sean Anderson [Mon, 21 Sep 2020 11:51:38 +0000 (07:51 -0400)]
riscv: Clear pending IPIs on initialization
Even though we no longer call smp_function if an IPI was not sent by
U-Boot, we still need to clear any IPIs which were pending from the
execution environment. Otherwise, secondary harts will busy-wait in
secondary_hart_loop, instead of relaxing.
Along with the previous commit ("riscv: Use a valid bit to ignore
already-pending IPIs"), this fixes SMP booting on the Kendryte K210.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
Sean Anderson [Mon, 21 Sep 2020 11:51:37 +0000 (07:51 -0400)]
riscv: Use a valid bit to ignore already-pending IPIs
Some IPIs may already be pending when U-Boot is started. This could be a
problem if a secondary hart tries to handle an IPI before the boot hart has
initialized the IPI device.
To be specific, the Kendryte K210 ROM-based bootloader does not clear IPIs
before passing control to U-Boot. Without this patch, the secondary hart
jumps to address 0x0 as soon as it enters secondary_hart_loop, and then
hangs in its trap handler.
This commit introduces a valid bit so secondary harts know when and IPI
originates from U-Boot, and it is safe to use the IPI API. The valid bit is
initialized to 0 by board_init_f_init_reserve. Before this, secondary harts
wait in wait_for_gd_init.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Liang <ycliang@andestech.com>
Sean Anderson [Mon, 21 Sep 2020 11:51:36 +0000 (07:51 -0400)]
riscv: Match memory barriers between send_ipi_many and handle_ipi
Without a matching barrier on the write side, the barrier in handle_ipi
does nothing. It was entirely possible for the boot hart to write to addr,
arg0, and arg1 *after* sending the IPI, because there was no barrier on the
sending side.
Fixes: 90ae281437 ("riscv: add option to wait for ack from secondary harts in smp functions") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Liang <ycliang@andestech.com>
Sean Anderson [Mon, 21 Sep 2020 11:51:35 +0000 (07:51 -0400)]
Revert "riscv: Clear pending interrupts before enabling IPIs"
Clearing MIP.MSIP is not guaranteed to do anything by the spec. In
addition, most existing RISC-V hardware does nothing when this bit is set.
The following commits "riscv: Use a valid bit to ignore already-pending
IPIs" and "riscv: Clear pending IPIs on initialization" should implement
the original intent of the reverted commit in a more robust manner.
Sean Anderson [Mon, 28 Sep 2020 14:52:29 +0000 (10:52 -0400)]
riscv: Update SiFive device tree for new CLINT driver
We currently do this in a u-boot specific dts, but hopefully we can get
these bindings added in Linux in the future.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
Sean Anderson [Mon, 28 Sep 2020 14:52:28 +0000 (10:52 -0400)]
riscv: Update Kendryte device tree for new CLINT driver
The interrupt controller property is removed from the clint binding because
the clint is not an interrupt-controller. That is, no other devices have an
interrupt which is controlled by the clint.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
Sean Anderson [Mon, 28 Sep 2020 14:52:27 +0000 (10:52 -0400)]
riscv: clk: Add CLINT clock to kendryte clock driver
Another "virtual" clock (in the sense that it isn't configurable). This
could possibly be done as a clock in the device tree, but I think this is a
bit cleaner.
Sean Anderson [Mon, 28 Sep 2020 14:52:26 +0000 (10:52 -0400)]
riscv: Rework Sifive CLINT as UCLASS_TIMER driver
This converts the clint driver from the riscv-specific interface to be a
DM-based UCLASS_TIMER driver. In addition, the SiFive DDR driver previously
implicitly depended on the CLINT to select REGMAP.
Unlike Andes's PLMT/PLIC (which AFAIK never have anything pass it a dtb),
the SiFive CLINT is part of the device tree passed in by qemu. This device
tree doesn't have a clocks or clock-frequency property on clint, so we need
to fall back on the timebase-frequency property. Perhaps in the future we
can get a clock-frequency property added to the qemu dtb.
Unlike with the Andes PLMT, the Sifive CLINT is also an IPI controller.
RISCV_SYSCON_CLINT is retained for this purpose.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
Sean Anderson [Mon, 28 Sep 2020 14:52:24 +0000 (10:52 -0400)]
riscv: Rework Andes PLMT as a UCLASS_TIMER driver
This converts the PLMT driver from the riscv-specific timer interface to be
a DM-based UCLASS_TIMER driver.
The clock-frequency/clocks properties are preferred over timebase-frequency
for two reasons. First, properties which affect a device should be located
near its binding in the device tree. Using timebase-frequency only really
makes sense when the cpu itself is the timer device. This is the case when
we read the time from a CSR, but not when there is a separate device.
Second, it lets the device use the clock subsystem which adds flexibility.
If the device is configured for a different clock speed, the timer can
adjust itself.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
Sean Anderson [Mon, 28 Sep 2020 14:52:23 +0000 (10:52 -0400)]
timer: Add a test for timer_timebase_fallback
To test this function, sandbox CPU must set cpu_platdata.timebase_freq on
bind. It also needs to expose a method to set the current cpu. I also make
some most members of cpu_sandbox_ops static.
On the timer side, the device tree property
sandbox,timebase-frequency-fallback controls whether sandbox_timer_probe
falls back to time_timebase_fallback or to SANDBOX_TIMER_RATE.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Mon, 28 Sep 2020 14:52:22 +0000 (10:52 -0400)]
timer: Add helper for drivers using timebase fallback
This function is designed to be used when a timer used to be initialized by
the cpu (e.g. RISC-V timers), but now is initialized by dm_timer_init. In
such a case, the timer may prefer to use the clocks and clock-frequency
properties, but should be able to fall back on using the cpu's
timebase-frequency.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
Sean Anderson [Mon, 28 Sep 2020 14:52:21 +0000 (10:52 -0400)]
riscv: Rework riscv timer driver to only support S-mode
The riscv-timer driver currently serves as a shim for several riscv timer
drivers. This is not too desirable because it bypasses the usual timer
selection via the driver model. There is no easy way to specify an
alternate timing driver, or have the tick rate depend on the cpu's
configured frequency. The timer drivers also do not have device structs,
and so have to rely on storing parameters in gd_t. Lastly, there is no
initialization call, so driver init is done in the same function which
reads the time. This can result in confusing error messages. To a user, it
looks like the driver failed when trying to read the time, whereas it may
have failed while initializing.
This patch removes the shim functionality from the riscv-timer driver, and
has it instead implement the former rdtime.c timer driver. This is because
existing u-boot users who pass in a device tree (e.g. qemu) do not create a
timer device for S-mode u-boot. The existing behavior of creating the
riscv-timer device in the riscv cpu driver must be kept. The actual reading
of the CSRs has been redone in the style of Linux's get_cycles64.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
Tom Rini [Fri, 25 Sep 2020 13:04:01 +0000 (09:04 -0400)]
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next
- Enhance the 'zboot' command to be more like 'bootm' with sub-commands
- The last series of ACPI core changes for programmatic generation of
ACPI tables
- Add all required ACPI tables for ApolloLake and enable ACPIGEN on
Chromebook Coral
- A feature minor enhancements to the 'hob' command
- Intel edison: Support for writing an xFSTK image via binman
Simon Glass [Sun, 6 Sep 2020 16:35:32 +0000 (10:35 -0600)]
binman: Show an error when a file is missing
The recent support for missing external binaries does not show an error
message when a file is genuinely missing (i.e. it is missing but not
marked as 'external'). This means that when -m is passed to binman, it
will never report a missing file.
Fix this and add a test.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Simon Glass [Tue, 22 Sep 2020 20:54:51 +0000 (14:54 -0600)]
x86: Add support for more than 8 MTRRs
At present the mtrr command only support 8 MTRRs. Some SoCs have more than
that. Update the implementation to support up to 10. Read the number of
MTRRs dynamically instead.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 20:54:50 +0000 (14:54 -0600)]
x86: Allow showing details about a HOB entry
Some HOBs include information that can be decoded. Add a -v option to the
hob command, to allow this to be displayed. Add the ability to decode a
resource descriptor.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 18:45:41 +0000 (12:45 -0600)]
x86: Move include of bitops out of ACPI region
At present linux/bitops.h is included in ACPI code. This is not needed and
can cause a problem in fls64.h since BITS_PER_LONG is not defined. Move
the #include into the part not used by ACPI.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 18:45:38 +0000 (12:45 -0600)]
x86: fsp: Show FSP-S or FSP-M address in fsp_get_header()
At present this function only supports FSP-M but it is also used to read
FSP-S, in which case FSP-M may be zero. Add support for showing whichever
address is present in the FSP binary.
Also change the debug() statements to log_debug() while here.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 18:45:37 +0000 (12:45 -0600)]
x86: fsp: Add more debugging for silicon init
If locating the FSP header hangs for whatever reason it is useful to see
where it got stuck. Add a debug print. Also show the address of the FSP-S
entry point as a sanity check.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
projects / u-boot.git / log