Nicolas Ferre [Wed, 25 Nov 2020 13:17:48 +0000 (14:17 +0100)]
arm: at91: configs: Enable CONFIG_SYS_NAND_USE_FLASH_BBT on all boards
As highlighted by Stefan in the commit e074d0f79b2e ("arm: at91:
gardena-smart-gateway-at91sam: Enable CONFIG_SYS_NAND_USE_FLASH_BBT")
it's important to use BBT when Linux enables it. We use it for a long
time on all our boards.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Stefan Roese <sr@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Tom Rini <trini@konsulko.com> Acked-by: Alexander Dahl <ada@thorsis.com>
Tom Rini [Wed, 16 Dec 2020 00:06:03 +0000 (19:06 -0500)]
Travis-CI: Drop support
Travis-CI is changing their support for FOSS (understandably) to have a
limited per-month number of build minutes. Unfortunately for us, the
matrix of jobs we run will exhaust that very quickly. Remove the yml
file. Thanks for all the builds, Travis-CI!
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Michael Walle [Sun, 20 Dec 2020 21:35:13 +0000 (22:35 +0100)]
board: kontron: sl28: reorder mmc devices
Since linux commit 2e6cde96873253fd9eb0f20afd8ffd18278cff75 ("arm64:
dts: ls1028a: make the eMMC and SD card controllers use fixed indices")
mmc0 is the eMMC and mmc1 is the SD card. Also swap it in u-boot to
avoid any confusion by the user and to be aligned with linux.
Tom Rini [Sun, 20 Dec 2020 19:55:59 +0000 (14:55 -0500)]
Merge tag 'efi-2021-01-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2021-01-rc4
* Provide a tool to create a file with UEFI variables to preseed UEFI
variable store.
* Make size of UEFI variable store configurable.
* Add man pages for commands 'bootefi' and 'button'.
Marek Szyprowski [Fri, 18 Dec 2020 10:43:45 +0000 (11:43 +0100)]
ARM: dts: meson: switch TFLASH_VDD_EN pin to open drain on Odroid-C4
For the proper reboot Odroid-C4 board requires to switch TFLASH_VDD_EN
pin to the high impedance mode, otherwise the board is stuck in the
middle of loading early stages of the bootloader from SD card.
This can be achieved by using the OPEN_DRAIN flag instead if the
ACTIVE_HIGH, what will leave the pin in input to achieve high state (pin
has the pull-up) and solve the issue.
Suggested-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add SPI Flash controller driver for Cortina Access
CAxxxx SoCs
Signed-off-by: Pengpeng Chen <pengpeng.chen@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Vignesh R <vigneshr@ti.com> CC: Tom Rini <trini@konsulko.com>
[jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Sean Anderson [Fri, 16 Oct 2020 22:57:53 +0000 (18:57 -0400)]
spi: dw: Add mem_ops
The designware ssi device has "broken" chip select behaviour [1], and needs
specific manipulation to use the built-in chip select. The existing fix is
to use an external GPIO for chip select, but typically the K210 has SPI3
directly connected to a flash chip with dedicated pins. This makes it
impossible to use the spi_xfer function to use spi, since the CS is
de-asserted in between calls. This patch adds an implementation of
exec_op, which gives correct behaviour when reading/writing spi flash.
This patch also rearranges the headers to conform to U-Boot style.
[1] https://lkml.org/lkml/2015/12/23/132
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Sean Anderson [Fri, 16 Oct 2020 22:57:52 +0000 (18:57 -0400)]
spi: dw: Document devicetree binding
This documentation has been taken from Linux commit 3d7db0f11c7a ("spi: dw:
Refactor mid_spi_dma_setup() to separate DMA and IRQ config"), immediately
before the file was deleted and replaced with a yaml version. Additional
compatible strings from newer versions have been added, as well as a few
U-Boot-specific ones.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Sean Anderson [Fri, 16 Oct 2020 22:57:51 +0000 (18:57 -0400)]
spi: dw: Add support for multiple CTRLR0 layouts
CTRLR0 can have several different layouts depending on the specific device
(dw-apb-ssi vs dwc-ssi), and specific parameters set during synthesis.
Update the driver to support three specific configurations: dw-apb-ssi with
SSI_MAX_XFER_SIZE=16, dw-apb-ssi with SSI_MAX_XFER_SIZE=32, and dwc-ssi.
dw-apb-ssi is the version of the device on Altera/Intel SoCFPGAs, MSCC
SoCs, and Canaan Kendryte K210 SoCs. This is the only version this driver
supported before this change. The register layout before version 3.23a is:
Note that DFS (Data Frame Size) is only 4 bits, limiting transfers to data
frames of 16 bits or less.
In version 3.23a, the SSI_MAX_XFER_SIZE parameter was introduced. This
parameter defaults to 16 (resulting in the same layout as prior versions),
but may also be set to 32. To allow setting longer data frame sizes, a new
DFS_32 register was introduced:
The old DFS field no longer controls the data frame size. To detect this
layout, we try writing 0xF to DFS. If we read back 0x0, then this device
has SSI_MAX_XFER_SIZE=32.
dwc-ssi is the version of the device on Intel Keem Bay SoCs and Canaan
Kendryte K210 SoCs. The layout of ctrlr0 is:
The semantics of the fields have not changed since the previous version.
However, SSI_MAX_XFER_SIZE is effectively always 32.
To support these different layouts, we model our approach on the one
which the Linux kernel has taken. During probe, the driver calls an init
function stored in driver_data. This init function is responsible for
determining the layout of CTRLR0, and supplying the update_cr0 function.
The style of and information behind this commit is based on the Linux MMIO
driver for these devices. Specific reference was made to the series adding
support for Intel Keem Bay SoCs [1].
Sean Anderson [Fri, 16 Oct 2020 22:57:50 +0000 (18:57 -0400)]
spi: dw: Add SoC-specific compatible strings
This adds SoC-specific compatible strings to all users of the designware
spi device. This will allow for the correct driver to be selected for each
device. Where it is publicly documented, a compatible string for the
specific device version has also been added. Devices without
publicly-documented device versions include MSCC SoCs, and Arc Socs. All
compatible strings except those for SoCFPGAs and some of the versioned
strings have been taken from Linux.
Since SSI_MAX_XFER_SIZE is determined at runtime, this is not strictly
necessary. However, it is a good cleanup and brings things closer to Linux.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Sean Anderson [Fri, 16 Oct 2020 22:57:49 +0000 (18:57 -0400)]
spi: dw: Rearrange struct dw_spi_priv
This should reduce the size of the struct, and also groups more similar
fields together.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Sean Anderson [Fri, 16 Oct 2020 22:57:46 +0000 (18:57 -0400)]
spi: dw: Use generic function to read reg address
Using an fdt-specific function causes problems when compiled with a live
tree.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Sean Anderson [Fri, 16 Oct 2020 22:57:45 +0000 (18:57 -0400)]
spi: dw: Rename "cs-gpio" to "cs-gpios"
This property is named differently than other SPI drivers with the same
property, as well as the property as used in Linux.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Sean Anderson [Fri, 16 Oct 2020 22:57:44 +0000 (18:57 -0400)]
spi: dw: Convert calls to debug to dev_*
This allows different log levels to be enabled or disabled depending on the
desired level of verbosity. In particular, it allows for general debug
information to be printed while excluding more verbose logging which may
interfere with timing.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Sean Anderson [Fri, 16 Oct 2020 22:57:43 +0000 (18:57 -0400)]
spi: dw: Fix driving MOSI low while recieving
The resting state of MOSI is high when nothing is driving it. If we drive
it low while recieving, it looks like we are transmitting 0x00 instead of
transmitting nothing. This can confuse slaves (like SD cards) which allow
new commands to be sent over MOSI while they are returning data over MISO.
The return of MOSI from 0 to 1 at the end of recieving a byte can look like
a start bit and a transmission bit to an SD card. This will cause the card
to become out-of-sync with the SPI device, as it thinks the device has
already started transmitting two bytes of a new command. The mmc-spi driver
will not detect the R1 response from the SD card, since it is sent too
early, and offset by two bits. This patch fixes transfer errors when using
SD cards with dw spi.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
U-Boot is able to erase bad mtd blocks on raw nand devices, but this
is not true for spinand flashes. Lets enable this feature for spinand
flashes as well. This is extemelly useful for flash testing.
Frieder Schrempf [Mon, 22 Jun 2020 13:16:33 +0000 (16:16 +0300)]
mtd: spinand: Do not erase the block before writing a bad block marker
Currently when marking a block, we use spinand_erase_op() to erase
the block before writing the marker to the OOB area. Doing so without
waiting for the operation to finish can lead to the marking failing
silently and no bad block marker being written to the flash.
In fact we don't need to do an erase at all before writing the BBM.
The ECC is disabled for raw accesses to the OOB data and we don't
need to work around any issues with chips reporting ECC errors as it
is known to be the case for raw NAND.
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Cc: stable@vger.kernel.org Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-4-frieder.schrempf@kontron.de
Frieder Schrempf [Mon, 22 Jun 2020 13:16:32 +0000 (16:16 +0300)]
mtd: spinand: Explicitly use MTD_OPS_RAW to write the bad block marker to OOB
When writing the bad block marker to the OOB area the access mode
should be set to MTD_OPS_RAW as it is done for reading the marker.
Currently this only works because req.mode is initialized to
MTD_OPS_PLACE_OOB (0) and spinand_write_to_cache_op() checks for
req.mode != MTD_OPS_AUTO_OOB.
Fix this by explicitly setting req.mode to MTD_OPS_RAW.
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-3-frieder.schrempf@kontron.de
Frieder Schrempf [Mon, 22 Jun 2020 13:16:31 +0000 (16:16 +0300)]
mtd: spinand: Stop using spinand->oobbuf for buffering bad block markers
For reading and writing the bad block markers, spinand->oobbuf is
currently used as a buffer for the marker bytes. During the
underlying read and write operations to actually get/set the content
of the OOB area, the content of spinand->oobbuf is reused and changed
by accessing it through spinand->oobbuf and/or spinand->databuf.
This is a flaw in the original design of the SPI NAND core and at the
latest from 13c15e07eedf ("mtd: spinand: Handle the case where
PROGRAM LOAD does not reset the cache") on, it results in not having
the bad block marker written at all, as the spinand->oobbuf is
cleared to 0xff after setting the marker bytes to zero.
To fix it, we now just store the two bytes for the marker on the
stack and let the read/write operations copy it from/to the page
buffer later.
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Cc: stable@vger.kernel.org Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-2-frieder.schrempf@kontron.de
Patrick Delaunay [Thu, 15 Oct 2020 15:18:17 +0000 (17:18 +0200)]
spi: migrate trace to dev and log macro in spi uclass
Define LOG_CATEGORY and change printf and pr_*
to dev_ (when dev is available) or log_ macro.
This patch adds the support of logging feature with log command
(filtering, display of device name in trace) and allows to
suppress traces via the syslog driver.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Fri, 23 Oct 2020 08:32:48 +0000 (14:02 +0530)]
dh_imx6: Switch to full DM-aware
Enable DM_SPI/DM_SPI_FLASH with a related config option.
Build fine, but not tested.
Cc: Ludwig Zenz <lzenz@dh-electronics.de> Cc: Andreas Geisreiter <ageisreiter@dh-electronics.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Hayes Wang [Wed, 16 Dec 2020 09:03:23 +0000 (17:03 +0800)]
eth/r8152: fix the aggregation issue
Remove the redundant setting for USB_RX_EARLY_SIZE. Besides, for
RTL8153B, it is necessary to notify the hardware of the changes
of the aggregation settings.
Ran Wang [Wed, 18 Nov 2020 07:49:02 +0000 (15:49 +0800)]
usb: xhci: fix lack of short packet event trb handling
For bulk IN transfer, the codes will set ISP flag to request event TRB
being generated by xHC for the case of short packet. So when encountering
buffer-cross-64K-boundary (which we will divide payload and enqueuqe
more than 1 transfer TRB), and the first TRB ends up with a short packet
condition it will trigger an short packet code transfer event per that
flag and cause more than 1 event TRB generated for this transfer.
However, current codes will only handle the first transfer event TRB
then mark current transfer completed, causing next transfer
failure due to event TRB mis-match.
Such issue has been observed on some Layerscape platforms (LS1028A,
LS1088A, etc) with USB ethernet device.
This patch adds a loop to make sure the event TRB for last transfer TRB
has been handled in time.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Thu, 3 Dec 2020 17:45:02 +0000 (19:45 +0200)]
x86: edison: Switch to DM_USB_GADGET
DM is the modern default approach for the drivers in U-Boot.
It also allows to configure code via Device Tree.
Move Intel Edison to use DM_USB_GADGET and drop hard coded values.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Thu, 3 Dec 2020 17:45:01 +0000 (19:45 +0200)]
x86: edison: Use dwc3-generic driver for Intel Edison
Use generic Synopsys DesignWare 3 driver on Intel Edison.
For now it's just a stub which allows future refactoring.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Thu, 3 Dec 2020 15:40:11 +0000 (17:40 +0200)]
x86: edison: BINMAN selection is specific to the board
The platforms based on Intel Tangier may have different requirements
how to create bootloader bundle to supply to a device. Currently
the BINMAN approach is for Intel Edison only.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Wed, 2 Dec 2020 10:35:32 +0000 (12:35 +0200)]
x86: edison: Add CPU to compatible string
Like in the rest of x86 boards append CPU to the board compatible string.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Fri, 27 Nov 2020 12:41:16 +0000 (14:41 +0200)]
x86: edison: Drop unneeded DM_PCI_COMPAT
None of the driver for Edison is using DM_PCI_COMPAT, hence drop it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Fri, 27 Nov 2020 12:40:48 +0000 (14:40 +0200)]
x86: tangier: Find proper memory region for relocation
It appears that U-Boot works by luck on Intel Edison board because the amount
of RAM is less than 1 GB and standard way of calculating the top of it work
for this configuration. However, this won't work if the amount of RAM is
different and split differently in address space. We have to find the suitable
window correctly.
Find proper memory region for relocation by scanning MMAP SFI table in
board_get_usable_ram_top() callback.
According to the address map documentation the Main Memory is guaranteed to lie
in the 0..2 GB range, that's why we limit search by this range.
Fixes: e71de54a4943 ("x86: Add Intel Tangier support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed a typo in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 9 Nov 2020 14:12:24 +0000 (07:12 -0700)]
x86: zimage: Update cmdline parameter to be an env var
With the updated changes to bootargs substitution[1], the zboot command
needs to be updated to get its command line from an environment variable
instead of a memory address. This is because the command-line string must
be updated to convert %U to ${uuid}, etc.
In any case it is more flexible to use a environment variable and it is
best to do this before the release to avoid a subsequent change.
Tom Rini [Tue, 15 Dec 2020 18:57:03 +0000 (13:57 -0500)]
Merge tag 'doc-2021-01-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Documentation fixes for v2020.01-rc4
Move several README files to reStructured text for the HTML documentation.
Describe register for global data on x86.
Allow building HTML documentation with Sphinx 3
Igor Opaniuk [Thu, 29 Oct 2020 10:59:19 +0000 (12:59 +0200)]
distro_bootcmd: set devtype for dhcp boot
Set $devtype for DHCP boot, which can be handy for the boot.scr
for detection of devtype used (for example, when the same boot.scr is
used for both mmc/dhcp boot):
if test ${devtype} = "dhcp"; then
...
fi
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
- Fix wrong amoswap t1 usage in startup.
- Reset the board after crash.
- Enable distro booting from an attached SCSI disk for QEMU.
- Support the optional header fields in efi header.
Marek Szyprowski [Mon, 14 Dec 2020 11:34:19 +0000 (12:34 +0100)]
usb: dwc3-meson-g12a: always configure dr-mode
dwc3_meson_g12a_force_mode() sets the dr-mode of the USB PHY. However
it skips setting the mode if it matches the one done during driver probe
(stored in private structure). This fails if the mode has been changed
to other value and then back to initial one. Fix this by configuring the
dr-mode always, regadless of the one set at the driver probe).
This fixes operation of USB gadget based drivers when they are initialized
for the second time.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Leo Yu-Chi Liang [Thu, 12 Nov 2020 02:09:52 +0000 (10:09 +0800)]
riscv: Fix efi header size for RV32
This patch depends on Atish's patch.
(https://patchwork.ozlabs.org/project/uboot/patch/20201013192331.3236458-1-atish.patra@wdc.com/)
Modify the size of the Optional Header "Windows-Specific Fields" to fit with the specification.
(https://docs.microsoft.com/en-us/windows/win32/debug/pe-format)
Atish Patra [Tue, 13 Oct 2020 19:23:31 +0000 (12:23 -0700)]
riscv: Fix efi header for RV32
RV32 should use PE32 format instead of PE32+ as the efi header format.
This requires following changes
1. A different header magic value
2. An additional parameter known as BaseOfData. Currently, it is set to
zero in absence of any usage.
Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
If an exception occurs on ARM or x86, we call panic() which will try to
reset the board. Do the same on RISC-V.
To avoid -Werror=format-zero-length move a '\n' to the string passed to
panic. We don't need a message here as depending on CONFIG_PANIC_HANG we
will either see
### ERROR ### Please RESET the board ###
or
resetting ...
as next message.
Reviewed-by: Rick Chen <rick@andestech.com> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Fri, 11 Dec 2020 20:55:17 +0000 (15:55 -0500)]
Merge tag 'u-boot-atmel-fixes-2021.01-b' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
Second set of u-boot-atmel fixes for 2021.01 cycle
This set includes very important fixes for: MMC booting on several
boards, drive strength on sam9x60ek mmc lines, compile issues for
timer.c old driver, removal of unwanted access to sam9x60 bit for
oscillator bypass mode, and eeproms read on sama5d2_icp.
projects / u-boot.git / log