From: Paul Barker Date: Mon, 16 Oct 2023 09:25:41 +0000 (+0100) Subject: arm: rmobile: Support RZ/G2L memory map X-Git-Url: http://git.dujemihanovic.xyz/img/static/gitweb.css?a=commitdiff_plain;h=eb4f1246f96974f0dd12c22e11f0b1139a34e3ee;p=u-boot.git arm: rmobile: Support RZ/G2L memory map The memory map for the RZ/G2L family differs from that of previous R-Car Gen3/Gen4 SoCs. A high level memory map can be seen in figure 5.2 (section 5.2.1) of the RZ/G2L data sheet rev 1.30 published May 12, 2023. A summary is included here (note that this is a 34-bit address space): * 0x0_0000_0000 - 0x0_0002_FFFF SRAM area * 0x0_0003_0000 - 0x0_0FFF_FFFF Reserved area * 0x0_1000_0000 - 0x0_1FFF_FFFF I/O register area * 0x0_2000_0000 - 0x0_2FFF_FFFF SPI Multi area * 0x0_3000_0000 - 0x0_3FFF_FFFF Reserved area * 0x0_4000_0000 - 0x1_3FFF_FFFF DDR area (4 GiB) * 0x1_4000_0000 - 0x3_FFFF_FFFF Reserved area Within the DDR area, the first 128 MiB are reserved by TrustedFirmware. The region from 0x43F00000 to 0x47DFFFFF inclusive is protected for use in TrustedFirmware/OP-TEE, but all other memory is included in the memory map. This reservation is the same as used in R-Car Gen3/Gen4 and RZ/G2{H,M,N,E} SoCs. DRAM information is initialised based on the data in the fdt. Signed-off-by: Paul Barker Reviewed-by: Biju Das Reviewed-by: Lad Prabhakar Reviewed-by: Marek Vasut --- diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index 45d6a0e2a2..ff8b0c7bae 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -10,11 +10,11 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o -obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o memmap-gen3.o -obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o -obj-$(CONFIG_RCAR_GEN4) += cpu_info-rcar.o +obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o +obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o memmap-gen3.o +obj-$(CONFIG_RCAR_GEN4) += cpu_info-rcar.o memmap-gen3.o obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o -obj-$(CONFIG_RZG2L) += cpu_info-rzg2l.o +obj-$(CONFIG_RZG2L) += cpu_info-rzg2l.o memmap-rzg2l.o ifneq ($(CONFIG_R8A779A0),) obj-$(CONFIG_ARMV8_PSCI) += psci-r8a779a0.o diff --git a/arch/arm/mach-rmobile/memmap-rzg2l.c b/arch/arm/mach-rmobile/memmap-rzg2l.c new file mode 100644 index 0000000000..a08d0ea08f --- /dev/null +++ b/arch/arm/mach-rmobile/memmap-rzg2l.c @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Renesas RZ/G2L family memory map tables + * + * Copyright (C) 2017 Marek Vasut + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#define RZG2L_NR_REGIONS 16 + +/* + * RZ/G2L supports up to 4 GiB RAM starting at 0x40000000, of + * which the first 128 MiB is reserved by TF-A. + */ +static struct mm_region rzg2l_mem_map[RZG2L_NR_REGIONS] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x03F00000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x47E00000UL, + .phys = 0x47E00000UL, + .size = 0xF8200000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = rzg2l_mem_map; + +DECLARE_GLOBAL_DATA_PTR; + +#define debug_memmap(i, map) \ + debug("memmap %d: virt 0x%llx -> phys 0x%llx, size=0x%llx, attrs=0x%llx\n", \ + i, map[i].virt, map[i].phys, map[i].size, map[i].attrs) + +void enable_caches(void) +{ + unsigned int bank, i = 0; + u64 start, size; + + /* Create map for register access */ + rzg2l_mem_map[i].virt = 0x0ULL; + rzg2l_mem_map[i].phys = 0x0ULL; + rzg2l_mem_map[i].size = 0x40000000ULL; + rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN; + debug_memmap(i, rzg2l_mem_map); + i++; + + /* Generate entries for DRAM in 32bit address space */ + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start = gd->bd->bi_dram[bank].start; + size = gd->bd->bi_dram[bank].size; + + /* Skip empty DRAM banks */ + if (!size) + continue; + + /* Mark memory reserved by ATF as cacheable too. */ + if (start == 0x48000000) { + /* Unmark protection area (0x43F00000 to 0x47DFFFFF) */ + rzg2l_mem_map[i].virt = 0x40000000ULL; + rzg2l_mem_map[i].phys = 0x40000000ULL; + rzg2l_mem_map[i].size = 0x03F00000ULL; + rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE; + debug_memmap(i, rzg2l_mem_map); + i++; + + start = 0x47E00000ULL; + size += 0x00200000ULL; + } + + rzg2l_mem_map[i].virt = start; + rzg2l_mem_map[i].phys = start; + rzg2l_mem_map[i].size = size; + rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE; + debug_memmap(i, rzg2l_mem_map); + i++; + } + + /* Zero out the remaining regions. */ + for (; i < RZG2L_NR_REGIONS; i++) { + rzg2l_mem_map[i].virt = 0; + rzg2l_mem_map[i].phys = 0; + rzg2l_mem_map[i].size = 0; + rzg2l_mem_map[i].attrs = 0; + debug_memmap(i, rzg2l_mem_map); + } + + if (!icache_status()) + icache_enable(); + + dcache_enable(); +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +}