From: Ovidiu Panait <ovpanait@gmail.com>
Date: Tue, 31 May 2022 18:14:29 +0000 (+0300)
Subject: microblaze: cache: introduce Kconfig options for icache/dcache sizes
X-Git-Url: http://git.dujemihanovic.xyz/img/static/gitweb.css?a=commitdiff_plain;h=84488fc69348367ee693ea4ab6affe3cbcae97a0;p=u-boot.git

microblaze: cache: introduce Kconfig options for icache/dcache sizes

Replace XILINX_DCACHE_BYTE_SIZE macro with two Kconfig symbols for
instruction and data caches sizes, respectively:
CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE
CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE

Also, get rid of the hardcoded value in icache_disable().

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-8-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/g)
---

diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index e362a34a79..d5c0afd935 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -65,8 +65,7 @@ void icache_enable(void)
 
 void icache_disable(void)
 {
-	/* we are not generate ICACHE size -> flush whole cache */
-	__invalidate_icache(0, 32768);
+	__invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE);
 
 	MSRCLR(0x20);
 }
@@ -78,7 +77,7 @@ void dcache_enable(void)
 
 void dcache_disable(void)
 {
-	__flush_dcache(0, XILINX_DCACHE_BYTE_SIZE);
+	__flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE);
 
 	MSRCLR(0x80);
 }
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index cd47b0f95b..6e3ffafa5f 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -99,7 +99,7 @@ uboot_sym_start:
 
 	/* Flush cache before enable cache */
 	addik	r5, r0, 0
-	addik	r6, r0, XILINX_DCACHE_BYTE_SIZE
+	addik	r6, r0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE
 	brlid	r15, flush_cache
 	nop
 
@@ -350,7 +350,7 @@ relocate_code:
 
 	/* Flush caches to ensure consistency */
 	addik	r5, r0, 0
-	addik	r6, r0, XILINX_DCACHE_BYTE_SIZE
+	addik	r6, r0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE
 	brlid	r15, flush_cache
 	nop
 
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index dba6226ce5..48e05333a6 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -57,7 +57,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 	       "(fake run for tracing)" : "");
 	bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
 
-	flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
+	flush_cache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE);
 
 	if (!fake) {
 		/*
diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig
index 98b4814b95..a6743cadf4 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -85,4 +85,20 @@ config SPL_XILINX_MICROBLAZE0_USE_WIC
 	bool
 	default XILINX_MICROBLAZE0_USE_WIC
 
+config XILINX_MICROBLAZE0_DCACHE_SIZE
+	int "Default data cache size"
+	default 32768
+	help
+	  This fallback size will be used when no dcache info can be found in
+	  the device tree, or when the data cache is flushed very early in the
+	  boot process, before device tree is available.
+
+config XILINX_MICROBLAZE0_ICACHE_SIZE
+	int "Default instruction cache size"
+	default 32768
+	help
+	  This fallback size will be used when no icache info can be found in
+	  the device tree, or when the instruction cache is flushed very early
+	  in the boot process, before device tree is available.
+
 endif
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 60ceb2c817..bae0f284fd 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -26,10 +26,6 @@
 # define CONFIG_SYS_MAX_FLASH_SECT	2048
 #endif
 
-#ifndef XILINX_DCACHE_BYTE_SIZE
-#define XILINX_DCACHE_BYTE_SIZE	32768
-#endif
-
 /* size of console buffer */
 #define	CONFIG_SYS_CBSIZE	512
 /* max number of command args */