From: Igor Prusov Date: Thu, 5 Oct 2023 08:54:27 +0000 (+0300) Subject: a1: clk: Add missing USB_PHY_IN and USB_PHY gates X-Git-Tag: v2025.01-rc5-pxa1908~823^2~13 X-Git-Url: http://git.dujemihanovic.xyz/img/static/gitweb.css?a=commitdiff_plain;h=7db7cce356a6f3f2e12a8fafc839452ef79c382f;p=u-boot.git a1: clk: Add missing USB_PHY_IN and USB_PHY gates We use this clocks in dwc3 driver. Signed-off-by: Igor Prusov Signed-off-by: Alexey Romanov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20231005085434.74755-7-avromanov@salutedevices.com Signed-off-by: Neil Armstrong --- diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c index 3aec42f33b..1075ba7333 100644 --- a/drivers/clk/meson/a1.c +++ b/drivers/clk/meson/a1.c @@ -238,6 +238,12 @@ static const struct meson_clk_info *meson_clocks[] = { [CLKID_FIXPLL_IN] = CLK_GATE("fixpll_in", A1_SYS_OSCIN_CTRL, 1, EXTERNAL_XTAL ), + [CLKID_USB_PHY_IN] = CLK_GATE("usb_phy_in", A1_SYS_OSCIN_CTRL, 2, + EXTERNAL_XTAL + ), + [CLKID_USB_PHY] = CLK_GATE("usb_phy", A1_SYS_CLK_EN0, 27, + CLKID_SYS + ), [CLKID_SARADC] = CLK_GATE("saradc", A1_SAR_ADC_CLK_CTR, 8, -ENOENT ),