From: Ye Li Date: Thu, 15 Jun 2023 10:09:12 +0000 (+0800) Subject: imx: misc: ele_mu: Update MU TR registers count X-Git-Url: http://git.dujemihanovic.xyz/img/static/gitweb.css?a=commitdiff_plain;h=71a21425d278a07ba263109fff0cba09ff30a157;p=u-boot.git imx: misc: ele_mu: Update MU TR registers count According to SRM, the Sentinel MU has 8 TR and 4 RR registers. All of them are used for ELE message. So update TR count to 8 and fix a typo in receive msg Reviewed-by: Peng Fan Signed-off-by: Ye Li Signed-off-by: Peng Fan --- diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c index 0d34b8c901..956f8a1eb2 100644 --- a/drivers/misc/imx_ele/ele_mu.c +++ b/drivers/misc/imx_ele/ele_mu.c @@ -22,7 +22,7 @@ struct imx8ulp_mu { #define MU_SR_TE0_MASK BIT(0) #define MU_SR_RF0_MASK BIT(0) -#define MU_TR_COUNT 4 +#define MU_TR_COUNT 8 #define MU_RR_COUNT 4 void mu_hal_init(ulong base) @@ -65,7 +65,7 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg) u32 val; int ret; - assert(reg_index < MU_TR_COUNT); + assert(reg_index < MU_RR_COUNT); debug("receivemsg sr 0x%x\n", readl(&mu_base->sr));